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publication number s25fs-s_00 revision 04 issue date november 6, 2013 s25fs-s family s25fs-s family cover sheet mirrorbit ? flash non-volatile memory 1.8-volt single suppl y with cmos i/o serial peripheral inte rface with multi-i/o s25fs128s 128 mb it (16 mbyte) s25fs256s 256 mb it (32 mbyte) data sheet (preliminary) notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product describ ed herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office.
this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary s tatus of this document indicates that product qual- ification has been completed, and that initial production has begun. due to the phases of the manufacturing process that requir e maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. publication number s25fs-s_00 revision 04 issue date november 6, 2013 features ? density ? 128 mbits (16 mbytes) ? 256 mbits (32 mbytes) ? serial peripheral interface (spi) ? spi clock polarity and phase modes 0 and 3 ? double data rate (ddr) option ? extended addressing: 24- or 32-bit address options ? serial command subset and footprint compatible with s25fl-a, s25fl-k, s25fl-p, and s25fl-s spi families ? multi i/o command subset and footprint compatible with s25fl-p, and s25fl-s spi families ? read ? commands: normal, fast, dual i/o, quad i/o, ddr quad i/o ? modes: burst wrap, continuous (xip), qpi ? serial flash discoverable parameters (sfdp) and common flash interface (cfi), for configuration information ? program ? 256- or 512-byte page programming buffer ? program suspend and resume ? erase ? hybrid sector option ? physical set of eight 4-kbyte sectors and one 32-kbyte sector at the top or bottom of address space with all remaining sectors of 64 kbytes ? uniform sector option ? uniform 64-kbyte or 256-kbyte blocks for software compatibility with higher density and future devices ? erase suspend and resume ? erase status evaluation ? 100,000 program-erase cycles on any sector, minimum ? 20 year data retention, typical ? security features ? one-time program (otp) array of 1024 bytes ? block protection: ? status register bits to control protection against program or erase of a contiguous range of sectors ? hardware and software control options ? advanced sector protection (asp) ? individual sector protection controlled by boot code or password ? option for password control of read access ? technology ? spansion 65 nm mirrorbit technology with eclipse ? architecture ? supply voltage ? 1.7v to 2.0v ? temperature range ? industrial (0 c to +85 c) ? automotive (?40 c to +105 c) ? packages (all pb-free) ? 8-lead soic 208 mil (soc008) - fs128s only ? wson 6x5 mm (wnd008) - fs128s only ? wson 6x8 mm (wnh008) - fs256s only ? 16-lead soic 300 mil (so3016- fs256s only) ? bga-24 6x8 mm ? 5x5 ball (fab024) footprint ? 4x6 ball (fac024) footprint ? known good die, and known tested die s25fs-s family mirrorbit ? flash non-volatile memory 1.8-volt single suppl y with cmos i/o serial peripheral inte rface with multi-i/o s25fs128s 128 mb it (16 mbyte) s25fs256s 256 mb it (32 mbyte) data sheet (preliminary)
4 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 1. performance summary table 1.1 maximum read rates command clock rate (mhz) mbytes / s read 50 6.25 fast read 133 16.5 dual read 133 33 quad read 133 66 table 1.2 maximum read rates ddr command clock rate (mhz) mbytes / s ddr quad i/o read 80 80 table 1.3 typical program and erase rates operation kbytes / s page programming (256-bytes page buffer) 712 page programming (512-bytes page buffer) 1080 4-kbyte physical sector erase (hybrid sector option 28 64-kbyte physical sector er ase (hybrid sector option) 450 256-kbyte sector erase (uniform logical sector option 450 table 1.4 typical current consumption (?40 c to +85 c) operation current (ma) serial read 50 mhz 10 serial read 133 mhz 20 quad read 133 mhz 60 quad ddr read 80 mhz 70 program 60 erase 60 standby 0.07
november 6, 2013 s25fs-s_00_04 s25fs-s family 5 data sheet (preliminary) table of contents features 1. performance summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 migration notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 other resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 hardware interface 3. signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 3.1 input/output summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 multiple input / output (mio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 chip select (cs#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 serial input (si) / io0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6 serial output (so) / io1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7 write protect (wp#) / io2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8 io3 / reset# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9 voltage supply (v dd ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.10 supply and signal ground (v ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11 not connected (nc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12 reserved for future use (rfu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13 do not use (dnu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4. signal protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 spi clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 command protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3 interface states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4 configuration register effects on the interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.5 data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 latch-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4 power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 5.5 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6. timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2 ac test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.4 sdr ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.5 ddr ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7. physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.1 soic 16-lead package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.2 8-connector packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.3 fab024 24-ball bga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.4 fac024 24-ball bga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 software interface 8. address space maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.2 flash memory array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.3 id-cfi address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.4 jedec jesd216 serial flash disco verable parameters (sfdp) space. . . . . . . . . . . . . . . 57 8.5 otp address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.6 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 9. data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.1 secure silicon region (otp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.2 write enable command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.3 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.4 advanced sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.5 recommended protection process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 10. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10.1 command set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.2 identification commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.3 register access commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.4 read memory array commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 10.5 program flash array commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 10.6 erase flash array commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 10.7 one-time program array commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.8 advanced sector protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.9 reset commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 11. embedded algorithm performance tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12. software interface reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.1 command summary by instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 12.3 serial flash discoverable parameters (sfdp) address map . . . . . . . . . . . . . . . . . . . . . . . 142 12.4 device id and common flash interface (id-cfi) addr ess map . . . . . . . . . . . . . . . . . . . . . 143 12.5 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ordering information 13. ordering part number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 14. contacting spansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 15. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
november 6, 2013 s25fs-s_00_04 s25fs-s family 7 data sheet (preliminary) figures figure 3.1 bus master and memory devices on the spi bus - single bit data path . . . . . . . . . . . . . . . 21 figure 3.2 bus master and memory devices on the spi bus - dual bit data path . . . . . . . . . . . . . . . . 22 figure 3.3 bus master and memory devices on the spi bus - quad bit data path. . . . . . . . . . . . . . . . 22 figure 4.1 spi sdr modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 4.2 spi ddr modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 4.3 stand alone instruction command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 4.4 single bit wide input command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 4.5 single bit wide output command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 4.6 single bit wide i/o command without latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 4.7 single bit wide i/o command with latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 figure 4.8 dual i/o command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 4.9 quad i/o command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 4.10 quad i/o read command in qpi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 figure 4.11 ddr quad i/o read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 4.12 ddr quad i/o read in qpi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 5.1 maximum negative overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 5.2 maximum positive overshoot wavefo rm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 figure 5.3 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 5.4 power-down and voltage drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 6.1 waveform element meanings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 6.2 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 6.3 input, output, and timing reference levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 6.4 reset low at the end of por . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 6.5 reset high at the end of por . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 6.6 por followed by hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 6.7 hardware reset when quad mode is not enabled and io3 / reset# is enabled . . . . . . . . . 39 figure 6.8 hardware reset when quad mode and io3 / reset# are enabled . . . . . . . . . . . . . . . . . . . . 40 figure 6.9 clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 6.10 spi single bit input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 6.11 spi single bit output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 6.12 spi sdr mio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 6.13 wp# input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 6.14 spi ddr input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 6.15 spi ddr output timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 6.16 spi ddr data valid window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 7.1 16-lead soic package (so3016), top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 7.2 soic 16-lead, 300-mil body width (so3016) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 7.3 8-pin plastic small outline package (soic8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 figure 7.4 8-connector package (wson 6x5), top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 7.5 soic 8-lead, 208 mil body width (soc008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 7.6 wson 8-contact 6x5 mm leadless (wnd008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 7.7 wson 8-contact 6x8 mm leadless (wnh008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 7.8 24-ball bga, 5x5 ball footprint (fab024), top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 7.9 ball grid array 24-ball 6x8 mm (fab024) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 7.10 24-ball bga, 4x6 ball footprint (fac024), top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 7.11 ball grid array 24-ball 6 x 8 mm (fac024) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 8.1 otp address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 9.1 sector protection control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 9.2 advanced sector protection overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 10.1 read identification (rdid) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 10.2 read identification (rdid) qpi mode command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 10.3 read quad identification (rdqid) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 10.4 rsfdp command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 10.5 rsfdp qpi mode command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) figure 10.6 read status register 1 (rdsr1) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 10.7 read status register 1 (rdsr1) qpi mode command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 10.8 read status register 2 (rdsr2) command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 10.9 read configuration register (rdcr) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 10.10 write registers (wrr) command sequence ? 8-data bits . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 10.11 write registers (wrr) command sequence ? 16-data bits . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 10.12 write registers (wrr) command sequence ? 16-data bits qpi mode. . . . . . . . . . . . . . . . 96 figure 10.13 write enable (wren) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 10.14 write enable (wren) command sequence qpi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 10.15 write disable (wrdi) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 10.16 write disable (wrdi) command sequence qpi mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 10.17 clear status register (clsr) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 10.18 clear status register (clsr) command sequence qpi mode . . . . . . . . . . . . . . . . . . . . . . 99 figure 10.19 program nvdlr (pnvdlr) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 10.20 write vdlr (wvdlr) command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 10.21 dlp read (dlprd) command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 10.22 enter 4-byte address mode (4bam b7h) command sequence . . . . . . . . . . . . . . . . . . . . . 100 figure 10.23 read any register read command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 10.24 read any register, qpi mode, cr2[7] = 0, comm and sequence . . . . . . . . . . . . . . . . . . . 102 figure 10.25 read any register, qpi mode, cr2[7] = 1 command sequence. . . . . . . . . . . . . . . . . . . . 102 figure 10.26 set burst length command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 04 figure 10.27 read command sequence (3-byte address, 03h or 13h) . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 10.28 fast read (fast_read) command sequence (3 -byte address, 0bh [cr2v[7]=0) . . . . . 106 figure 10.29 dual i/o read command sequence (3-byte addre ss, bbh [cr2v[7]=0]) . . . . . . . . . . . . . 107 figure 10.30 dual i/o read command sequence (4-byte addre ss, bbh [cr2v[7]=1]) . . . . . . . . . . . . . 107 figure 10.31 dual i/o continuous read command sequence (4-byte address [cr2v[7]=1]) . . . . . . . . 108 figure 10.32 quad i/o read command sequence (3-byte addre ss, ebh [cr2v[7]=0]). . . . . . . . . . . . . 109 figure 10.33 quad i/o read command sequence (3-byte address, ebh [cr2v[7]=0]) qpi mode . . . . 109 figure 10.34 continuous quad i/o read command sequence (3-byte address) . . . . . . . . . . . . . . . . . . 109 figure 10.35 quad i/o read command sequence (4-byte addr ess, ech or ebh [cr2v[7]=1]) . . . . . . 110 figure 10.36 continuous quad i/o read command sequence (4-byte address) . . . . . . . . . . . . . . . . . . 110 figure 10.37 quad i/o read command sequence (4-byte address, ech or ebh [cr2v[7]=1]) qpi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 10.38 ddr quad i/o read initial access (3-byte addre ss, edh [cr2v[7]=0) . . . . . . . . . . . . . . . 112 figure 10.39 continuous ddr quad i/o read subsequent access (3-byte address) . . . . . . . . . . . . . . 112 figure 10.40 ddr quad i/o read initial access (4-byte addr ess, eeh or edh [cr2v[7]=1]) . . . . . . . . 112 figure 10.41 ddr quad i/o read initial access (4-byte address, eeh or edh [cr2v[7]=1]) qpi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 10.42 continuous ddr quad i/o read subsequent access (4-byte address) . . . . . . . . . . . . . . 113 figure 10.43 page program (pp 02h or 4pp 12h) command sequence. . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 10.44 page program (pp 02h or 4pp 12h) qpi mode command sequence . . . . . . . . . . . . . . . . 114 figure 10.45 parameter sector erase (p 4e 20h or 4p4e 21h) command sequence . . . . . . . . . . . . . . . 115 figure 10.46 parameter sector erase (p4e 20h or 4p4e 21h) qpi mode command sequence . . . . . . 116 figure 10.47 sector erase (se d8h or 4se dch) command sequen ce . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 10.48 sector erase (se d8h or 4se dch) qpi mode co mmand sequence . . . . . . . . . . . . . . . . 117 figure 10.49 bulk erase command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 10.50 bulk erase command sequence qpi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 10.51 ees comm and sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 10.52 ees qpi mode command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9 figure 10.53 program or erase suspend command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 10.54 program or erase suspend command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 10.55 program or erase suspend command sequence qpi mode . . . . . . . . . . . . . . . . . . . . . . . 122 figure 10.56 erase or program resume command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 10.57 erase or program resume command sequence qpi mode . . . . . . . . . . . . . . . . . . . . . . . 122 figure 10.58 asprd command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
november 6, 2013 s25fs-s_00_04 s25fs-s family 9 data sheet (preliminary) figure 10.59 aspp comm and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 10.60 dybrd command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 10.61 dybrd qpi mode command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 10.62 dybwr command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 10.63 dybwr qpi mode command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 10.64 ppbrd command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 10.65 ppbp command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 10.66 ppb erase command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 10.67 ppb lock regi ster read command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 10.68 ppb lock bit write command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9 figure 10.69 password read command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9 figure 10.70 password program command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 10.71 password unlock command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 10.72 software reset command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 10.73 software reset command sequence qpi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 10.74 mode bit reset command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 10.75 mode bit reset command sequence qpi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) tables table 1.1 maximum read rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1.2 maximum read rates ddr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1.3 typical program and erase rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1.4 typical current consumption (?40c to +85c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2.1 spansion spi families comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3.1 signal list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4.1 interface states summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 5.2 latch-up specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 5.3 fs-s power-up / power-down voltage and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 5.4 fs-s dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 6.1 ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 6.2 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 6.3 hardware reset parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 6.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 6.5 ac characteristics 80 mhz operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 8.1 s25fs256s sector address map, bottom 4-kb sect ors, 64-kb physical uniform sectors . 55 table 8.2 s25fs256s sector address map, top 4-kb se ctors, 64-kb physical uniform sectors . . . . 55 table 8.3 s25fs256s sector address map, uniform 64-kb physical sectors . . . . . . . . . . . . . . . . . . . 55 table 8.4 s25fs256s sector address map, bottom 4-kb se ctors, 256-kb logical uniform sectors . 55 table 8.6 s25fs256s sector address map, uniform 256-kb logical sectors . . . . . . . . . . . . . . . . . . . 56 table 8.7 s25fs128s sector and memory address map, bottom 4-kb sectors . . . . . . . . . . . . . . . . . 56 table 8.8 s25fs128s sector and memory address map, top 4-kb sectors . . . . . . . . . . . . . . . . . . . . 56 table 8.9 s25fs128s sector and memory address map, uniform 64-kb blocks . . . . . . . . . . . . . . . . 56 table 8.5 s25fs256s sector address map, top 4-kb se ctors, 256-kb logical uniform sectors . . . . 56 table 8.10 s25fs128s sector addre ss map, bottom 4-kb sectors, 2 56-kb logical uniform sectors . 57 table 8.11 s25fs128s sector address map, top 4-kb sectors, 256-kb logical uniform sectors . . . . 57 table 8.12 s25fs128s sector and memory address map, uniform 256-kb blocks . . . . . . . . . . . . . . . 57 table 8.13 otp address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 8.14 status register 1 non-volatile (sr1nv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 8.15 status register 1 volatile (sr1v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 8.16 status register 2 volatile (sr2v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 8.17 configuration register 1 non-vola tile (cr1nv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 8.18 configuration register 1 volatile (cr1v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 8.19 configuration register 2 non-vola tile (cr2nv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 8.20 latency code (cycles) versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 table 8.21 configuration register 2 volatile (cr2v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 8.22 configuration register 3 non-vola tile (cr3nv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 8.23 configuration register 3 volatile (cr3v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 8.24 configuration register 4 non-vola tile (cr4nv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 8.25 output impedance control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 8.26 configuration register 4 volatile (cr4v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 8.27 asp register (aspr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 8.28 password register (pass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 8.29 ppb lock register (ppbl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 8.30 ppb access register (ppbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 8.31 dyb access register (dybar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 8.32 non-volatile data learning register (nvdlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 8.33 volatile data learning register (vdlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 9.1 upper array start of protection (tbprot_o = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 9.2 lower array start of protection (tbprot_o = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 9.3 sector protection states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 10.1 s25fs-s family command set (sorted by function) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 10.2 block protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
november 6, 2013 s25fs-s_00_04 s25fs-s family 11 data sheet (preliminary) table 10.3 register address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 10.4 example burst wrap sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 10.5 commands allowed during program or erase suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 11.1 program and erase performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 11.2 program or erase suspend ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 12.1 s25fs-s family command set (sorted by instruction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 12.2 status register 1 non-volatile (sr1nv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 12.3 status register 1 volatile (sr1v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 12.4 status register 2 volatile (sr2v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 12.5 configuration register 1 non-vola tile (cr1nv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 12.6 configuration register 1 volatile (cr1v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 12.7 configuration register 2 non-vola tile (cr2nv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 12.8 configuration register 2 volatile (cr2v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 12.9 configuration register 3 non-vola tile (cr3nv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 12.10 configuration register 3 volatile (cr3v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 12.11 configuration register 4 non-volatile (cr4nv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 12.12 configuration register 4 volatile (cr4v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 12.13 asp regi ster (aspr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 12.14 password re gister (pass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 12.15 ppb lock regi ster (ppbl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 12.16 ppb access register (ppbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 12.17 dyb access register (dybar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 12.18 non-volatile data learning register (nvdlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 12.19 volatile data learning register (vdlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 12.20 sfdp overview map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 12.21 sfdp header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 12.22 manufacturer and device id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 12.23 cfi query identification string. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 12.24 cfi system interface string. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 12.25 device geometry definition for bottom boot init ial delivery state . . . . . . . . . . . . . . . . . . . 145 table 12.26 cfi primary vendor-specific extended query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 12.27 cfi alternate vendor-specific extended query header . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 12.28 cfi alternate vendor-specific extended query parameter 0 . . . . . . . . . . . . . . . . . . . . . . . 147 table 12.29 cfi alternate vendor-specific extended query parameter 80h address options . . . . . . . 147 table 12.30 cfi alternate vendor-specific extended query parameter 84h suspend commands . . . . 148 table 12.31 cfi alternate vendor-specific extended query parameter 88h data protection . . . . . . . . 148 table 12.32 cfi alternate vendor-specific extended query parameter 8ch reset timing . . . . . . . . . . 148 table 12.33 cfi alternate vendor-specific extended query parameter f0h rfu . . . . . . . . . . . . . . . . . 149 table 12.34 cfi alternate vendor-specific extended quer y parameter a5h, jedec sfdp . . . . . . . . . 149
12 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 2. overview 2.1 general description the spansion s25fs-s family devices are fl ash non-volatile memory products using: ? mirrorbit technology - that stores two da ta bits in each memory array transistor ? eclipse architecture - that dramatically improves program and erase performance ? 65 nm process lithography thes25fs-s family connects to a host system via a serial peripheral interface (spi ). traditional spi single bit serial input and output (single i/o or sio) is suppor ted as well as optional 2-bit (dual i/o or dio) and 4-bit wide quad i/o (qio) or quad peripheral interface (qpi ) serial commands. this multiple width interface is called spi multi-i/o or mio. in addi tion, there are double data rate (ddr) read commands for qio and qpi that transfer address and read data on both edges of the clock. the fs-s eclipse architecture featur es a page programming buffer that allows up to 512 bytes to be programmed in one operation, resulting in faster e ffective programming and erase than prior generation spi program or erase algorithms. executing code directly from flash me mory is often called execute-in-place or xip. by using s25fs-s family devices at the higher clock rates supported, with qu ad or ddr quad commands, the instruction read transfer rate can match or exceed traditional parallel interf ace, asynchronous, nor flash memories, while reducing signal count dramatically. the s25fs-s family products offer high densities coupled with the flexibility and fa st performance required by a variety of mobile or em bedded applications. t hey are an excellent solution fo r systems with li mited space, signal connections, and power. they are ideal for co de shadowing to ram, executi ng code directly (xip), and storing reprogrammable data.
november 6, 2013 s25fs-s_00_04 s25fs-s family 13 data sheet (preliminary) 2.2 migration notes 2.2.1 features comparison the s25fs-s family is command subs et and footprint compatible with prior generation fl-s, fl-k, and fl-p families. however, the power supply an d interface voltages are nominal 1.8v. notes: 1. the 256b program page option only for 128-mb and 256-mb density fl-s devices. 2. the fl-p column indicates fl129p mio spi device (for 128-mb density), fl128p does not support mio, otp, or 4-kb sectors. 3. 64-kb sector erase option only for 128-mb/256-mb density fl-p, fl-s and fs-s devices. 4. the fl-k family devices can erase 4-kb sectors in groups of 32 kb or 64 kb. 5. 512-mb/1-gb fl-s devices support 256-kb sector only. 6. only 128-mb/256-mb density fl-s devices have 4-kb parameter sector option. 7. refer to individual data sheets for further details. table 2.1 spansion spi families comparison parameter fs-s fl-s fl-k fl-p technology node 65 nm 65 nm 90 nm 90 nm architecture mirrorbit eclipse mirrorbit eclipse floating gate mirrorbit density 128 mb, 256 mb 128 mb, 256 mb, 512 mb, 1 gb 4 mb - 128 mb 32 mb - 256 mb bus width x1, x2, x4 x1, x2, x4 x1, x2, x4 x1, x2, x4 supply voltage 1.7v - 2.0v 2.7v - 3.6v / 1.65v - 3.6v v io 2.7v - 3.6v 2.7v - 3.6v normal read speed (sdr) 6 mb/s (50 mhz) 6 mb/s (50 mhz) 6 mb/s (50 mhz) 6 mb/s (40 mhz) fast read speed (sdr) 16.5 mb/s (133 mhz) 17 mb/s (133 mhz) 13 mb/s (104 mhz) 13 mb/s (104 mhz) dual read speed (sdr) 33 mb/s (133 mhz) 26 mb/s (104 mhz) 26 mb/s (104 mhz) 20 mb/s (80 mhz) quad read speed (sdr) 66 mb/s (133 mhz) 52 mb/s (104 mhz) 52 mb/s (104 mhz) 40 mb/s (80 mhz) quad read speed (ddr) 80 mb/s (80 mhz) 66 mb/s (66 mhz) program buffer size 256b / 512b 256b / 512b 256b 256b erase sector size 64 kb / 256 kb 64 kb / 256 kb 4 kb / 32 kb / 64 kb 64 kb / 256 kb parameter sector size 4 kb (option) 4 kb (option) 4 kb 4 kb sector erase rate (typ.) 500 kb/s 500 kb/s 136 kb/s (4 kb) 437 kb/s (64 kb) 130 kb/s page programming rate (typ.) 0.71 mb/s (256b) 1.08 mb/s (512b) 1.2 mb/s (256b) 1.5 mb/s (512b) 365 kb/s 170 kb/s otp 1024b 1024b 768b (3x256b) 506b advanced sector protection yes yes no no auto boot mode no yes no no erase suspend/resume yes yes yes no program suspend/resume yes yes yes no operating temperature ?40c to +85c / +105c ?40c to +85c / +105c ?40c to +85c ?40c to +85c / +105c
14 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 2.2.2 known differences from prior generations 2.2.2.1 error reporting fl-k and fl-p memories either do no t have error status bits or do not set them if program or erase is attempted on a protected sect or. the fs-s and fl-s families do have error reporting status bits for program and erase operations. these can be set when there is an in ternal failure to program or erase, or when there is an attempt to program or erase a protected sector. in these cases the program or erase operation did not complete as requested by the command. the p_err or e_err bits and the wip bit will be set to and remain 1 in sr1v. the clear status register command must be sent to clear the errors and return the device to standby state. 2.2.2.2 secure silicon region (otp) the fs-s size and format (address map) of the one-time program area is different from fl-k and fl-p generations. the method for protecting each portion of the otp area is different. for additional details see secure silicon region (otp) on page 76 . 2.2.2.3 configuration register freeze bit the configuration register 1 freeze bit cr1v[0], locks th e state of the block protection bits (sr1nv[4:2] and sr1v[4:2]), tbparm_o bit (cr1nv[2]), and tbprot_o bi t (cr1nv[5]), as in prior generations. in the fs-s and fl-s families the freeze bit also locks th e state of the configurat ion register 1 bpnv_o bit (cr1nv[3]), and the secure silicon region (otp) area. 2.2.2.4 sector erase commands the command for erasing a 4-kbyte sect or is supported only for use on 4- kbyte parameter se ctors at the top or bottom of the fs-s device address space. the command for erasing an 8-kbyte area (t wo 4-kbyte sectors) is not supported. the command for erasing a 32-kbyte area (e ight 4-kbyte sectors) is not supported. the sector erase command (se) for fs-s 64-kbyte sect ors is supported when the configuration option for uniform 64-kbyte sector is selected or, when the hybrid configuration opt ion for 4-kbyte parameter sectors with 64-kbyte uniform sectors is used . when the hybrid option is in us e, the 64-kbyte erase command may be used to erase the 32-kbyte of addre ss space adjacent to the group of eight 4-kbyte sector s. the 64-kbyte erase command in this case is erasing the 64-kbyte sect or that is partially overlaid by the group of eight 4-kbyte sectors without affe cting the 4-kbyte sectors. this provides erase control over the 32 kbytes of address space without also forcing the erase of the 4- kbyte sectors. this is different behavior than implemented in the fl-s family. in the fl-s family , the 64-kbyte sector erase command can be applied to a 64-kbyte block of 4-kbyte sectors to erase the entire block of parameter se ctors in a single operation. in the fs-s, the parameter sectors do not fill an entire 64-kb yte block so only the 4-kbyte parameter sector erase (20h) is used to erase parameter sectors. the erase command for a 256-kbyte sector replaces t he 64-kbyte erase command when the configuration option for 256-kbyte uniform logical sectors is used. 2.2.2.5 deep power-down the deep power-down (dpd) function is not suppo rted in the fs-s and fl-s family devices. 2.2.2.6 wrr single register write in some legacy spi devices, a writ e registers (wrr) command with only one data byte would update status register 1 and clear some bits in configuration register 1, including the quad mode bit. this could result in unintended exit from quad mode. th e s25fs-s family only updates st atus register 1 when a single data byte is provided. the configuration register 1 is not modified in this case.
november 6, 2013 s25fs-s_00_04 s25fs-s family 15 data sheet (preliminary) 2.2.2.7 other legacy commands not supported ? autoboot related commands ? bank address related commands ? dual output read ? quad output read ? quad page program (qpp) - replaced by page program in qpi mode ? ddr fast read ? ddr dual i/o read 2.2.2.8 new features the fs-s family introduces new featur es to spansion spi category memories: ? single 1.8v power supply for core and i/o voltage. ? configurable initial read la tency (number of dummy cycles) for faster in itial access time or higher clock rate read commands ? quad peripheral interface (qpi, 4-4-4) read mode in which all transfers are 4 bits wide, including instructions ? jedec jesd216 standard, serial flash discoverable pa rameters (sfdp) that provide device feature and configuration information. ? evaluate erase status command to determine if the last erase operation on a sector completed successfully. this command can be used to detect inco mplete erase due to power loss or other causes. this command can be he lpful to flash file system software in file system recovery after a power loss. ? advanced sector protection (asp) permanent protection. a bit is added to the asp register to provide the option to make protection of the persistent protec tion bits (ppb) permanent. also, when one of the two asp protection modes is selected, all otp configuratio n bits in all registers ar e protected from further programming so that all otp configuration settings are made permanent. the otp address space is not protected by the sele ction of an asp protection mo de. the freeze bit (cr1v[0]) may be used to protect the otp address space.
16 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 2.3 glossary bcd (binary coded decimal) a value in which each 4-bit nibb le represents a decimal numeral. command all information transferred between the host system and memory during one period while cs# is low. this includes the instruction (sometimes called an operation code or opcode) and any required address, mode bi ts, latency cycles, or data. ddp (dual die package) two die stacked within the same package to increase the memory capacity of a single package. often also referred to as a multi-chip package (mcp). ddr (double data rate) when input and output are latched on every edge of sck. flash the name for a type of electrical erase programmable read only memory (eeprom) that erases large blocks of memory bits in parallel, making the erase operation much faster than early eeprom. high a signal voltage level v ih or a logic level representing a binary one (1). instruction the 8-bit code indicating the function to be performed by a command (sometimes called an operation code or opcode). the instruction is always the first 8 bits transferred from host system to the memory in any command. low a signal voltage level v il or a logic level representing a binary zero (0). lsb (least significant bit) generally the right most bit, with the lowest order of magnitude value, within a group of bits of a register or data value. msb (most significant bit) generally the left most bit, with the highest order of magnitude value, within a group of bits of a register or data value. n/a (not applicable) a value is not relevant to situation described. non-volatile no power is needed to maintain data stored in the memory. opn ordering part number. the alphanumeric string specifying the memory device type, density, package, factory non-volatile configuration, etc. used to select the desired device. page 512-byte or 256-byte aligned and length group of data. the size assigned for a page depends on the ordering part number. pcb printed circuit board. register bit references are in the format: register_name[bit_number] or register_name[bit_range_msb: bit_range_lsb] sdr (single data rate) when input is latched on the rising edge and output on the falling edge of sck. sector erase unit size; depending on device model and sector location this may be 4 kbytes, 64 kbytes or 256 kbytes. write an operation that changes data within volatile or non-volatile registers bits or non-volatile flash memory. when changing non-volatile data, an erase and reprogramming of any unchanged non-volatile data is done, as part of the operation, such that the non-volatile data is modified by the write operation, in the sa me way that volatile data is modified ? as a single operation. the non-volatile data appears to the host system to be updated by the single write command, without the need for separate commands for erase and reprogram of adjacent, but unaffected data.
november 6, 2013 s25fs-s_00_04 s25fs-s family 17 data sheet (preliminary) 2.4 other resources 2.4.1 links to software http://www.spansion.com/ support/pages/support.aspx 2.4.2 links to application notes http://www.spansion.com/support/technical documents/pages/applicationnotes.aspx 2.4.3 specification bulletins specification bulletins provide information on temporar y differences in feature description or parametric variance since the publication of the last full data sheet. contact your local sales office for details. obtain the latest list of company locations and contact information at: http://www.spansion.com/about/pages/locations.aspx
18 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) hardware interface serial peripheral interface with multiple input / output (spi-mio) many memory devices connect to their host system with separate parallel control, address, and data signals that require a large number of signal connections and la rger package size. the large number of connections increase power consumption due to so many signals switching and the larger package increases cost. the s25fs-s family reduces the number of signals for connection to the host system by serially transferring all control, address, and data information over 4 to 6 signals. this reduces the co st of the memory package, reduces signal switching power, and either reduces the host connection count or frees host connectors for use in providing other features. the s25fs-s family uses the industry standard single bi t serial peripheral interface (spi) and also supports optional extension commands for 2-bit (dual) and 4-bi t (quad) wide serial transfers. this multiple width interface is called spi multi-i/o or spi-mio. 3. signal descriptions 3.1 input/output summary table 3.1 signal list signal name type description sck input serial clock. cs# input chip select. si / io0 i/o serial input for single bit data commands or io0 for dual or quad commands. so / io1 i/o serial output for single bit data commands. io1 for dual or quad commands. wp# / io2 i/o write protect when not in quad mode (cr1v[1] = 0 and sr1nv[7] = 1). io2 when in quad mode (cr1v[1] = 1). the signal has an internal pull-up resistor and may be left unconnected in the host system if not used for quad commands or writ e protection. if write protection is enabled by sr1nv[7] = 1 and cr1v[1] = 0, the host system is required to drive wp# high or low during a wrr or wrar command. io3 / reset# i/o io3 in quad-i/o mode, when configuration regi ster 1 quad bit, cr1v[1] =1, and cs# is low. reset# when enabled by cr2v[5]=1 and not in quad-i/o mode, cr1v[1] = 0, or when enabled in quad mode, cr1v[1] = 1 and cs# is high. the signal has an internal pull-up resistor and may be left unconnected in the host system if not used for quad commands or reset#. v dd supply power supply. v ss supply ground. nc unused not connected. no device internal signal is connec ted to the package connector nor is there any future plan to use the connecto r for a signal. the connection may safely be used for routing space for a signal on a printe d circuit board (pcb). however, any signal connected to an nc must not have voltage levels higher than v dd . rfu reserved reserved for future use. no device internal signal is currently connected to the package connector but there is potential future use of the connector for a signal. it is recommended to not use rfu connectors for pcb routing channels so that the pcb may take advantage of future enhanced features in compatible footprint devices. dnu reserved do not use. a device internal signal may be c onnected to the package connector. the connection may be used by spansion for test or other purposes and is not intended for connection to any host system signal. any dnu si gnal related function will be inactive when the signal is at v il . the signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to v ss . do not use these connections for pcb signal routing channels. do not connect any host system signal to this connection.
november 6, 2013 s25fs-s_00_04 s25fs-s family 19 data sheet (preliminary) 3.2 multiple input / output (mio) traditional spi single bit wide commands (single or sio) send information from the host to the memory only on the serial input (si) signal. data may be sent back to the host serially on the serial output (so) signal. dual or quad input / output (i/o) commands send in structions to the memory only on the si/io0 signal. address or data is sent from the host to the memory as bit pairs on io0 and io1 or four bit (nibble) groups on io0, io1, io2, and io 3. data is returned to the host similarly as bit pairs on io0 and io1 or four bit (nibble) groups on io0, io1, io2, and io3. qpi mode transfers all instructions, addr ess, and data from the host to the me mory as four bit (nibble) groups on io0, io1, io2, and io3. data is re turned to the host similarly as four bi t (nibble) groups on io0, io1, io2, and io3. 3.3 serial clock (sck) this input signal provides the synchronization reference fo r the spi interface. instructions, addresses, or data input are latched on the rising edge of the sck signal. da ta output changes after the falling edge of sck, in sdr commands, and after every edge in ddr commands. 3.4 chip select (cs#) the chip select signal indicates when a command is transferring information to or from the device and the other signals are relevant for the memory device. when the cs# signal is at the logic hi gh state, the device is not selected and all input signals are ignored and all output signals are high impedance. the device will be in the standby power mode, unless an internal embedded operation is in progress. an embedded ope ration is indicated by the status register 1 write-in-progress bit (sr1v[1]) se t to 1, until the operation is completed. some example embedded operations are: program, erase, or write registers (wrr) operations. driving the cs# input to the logic low state enables the device, placing it in the active power mode. after power-up, a falling edge on cs# is required prior to the start of any command. 3.5 serial input (si) / io0 this input signal is used to transfer data serially into the device. it receives instructions, addresses, and data to be programmed. values are latched on the rising edge of serial sck clock signal. si becomes io0 - an input and output during dual and quad commands for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial sck clock signal) as well as shifting out data (on the falling edge of sck, in sdr comma nds, and on every edge of sck, in ddr commands). 3.6 serial output (so) / io1 this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of the serial sck clock signal. so becomes io1 - an input and output during dual and quad commands for receiving addresses, and data to be programmed (values latched on rising edge of serial sck clock signal) as well as shifting out data (on the falling edge of sck, in sdr commands, a nd on every edge of sck, in ddr commands). 3.7 write protect (wp#) / io2 when wp# is driven low (v il ), during a wrr or wrar command and while the status register write disable (srwd_nv) bit of status register 1 (sr1nv[7]) is set to a 1, it is not possible to write to status register 1 or configuration register 1 related register s. in this situation, a wrr command is ignored, a wrar command selecting sr1nv, sr1v, cr1nv, or cr1v is ignored, and no error is set. this prevents any alteration of the block protection se ttings. as a consequence, all the data bytes in the memory area that are protected by the block protecti on feature are also hardwar e protected against data modification if wp# is low during a wrr or wrar command with srwd_nv set to 1.
20 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) the wp# function is not available when the quad m ode is enabled (cr1v[1]=1). the wp# function is replaced by io2 for input and output during quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the sck signal) as well as shifting out data (on the falling edge of sck, in sdr commands, and on every edge of sck, in ddr commands). wp# has an internal pull-up resistanc e; when unconnected, wp# is at v ih and may be left unconnected in the host system if not used for quad mode or protection. 3.8 io3 / reset# io3 is used for input and output during quad mode ( cr1v[1]=1) for receiving addresses, and data to be programmed (values are latched on rising edge of the sck signal) as well as shifting out data (on the falling edge of sck, in sdr commands, and on every edge of sck, in ddr commands). the io3 / reset# signal may also be used to initiate the hardware re set function when the reset feature is enabled by writing configuration register 2 non-volat ile bit 5 (cr2v[5]=1). the input is only treated as reset# when the device is not in quad-i/o mode, cr1v[1 ] = 0, or when cs# is high. when quad i/o mode is in use, cr1v[1]=1, and the device is selected wit h cs# low, the io3 / reset# is used only as io3 for information transfer. when cs# is high, the io3 / reset# is not in use for information transfer and is used as the reset# input. by conditioning the reset operatio n on cs# high during quad mode, the reset function remains available during quad mode. when the system enters a reset conditio n, the cs# signal must be driven high as part of the reset process and the io3 / reset# signal is driven low. when cs# goes high the io3 / reset# input transitions from being io3 to being the reset# input. the reset condition is then detected when cs# remains high and the io3 / reset# signal remains low for t rp . if a reset is not intended, the system is required to actively drive io3 / reset# to high along with cs# being driven high at the end of a transfer of data to the memory. following transfers of data to the host syste m, the memory will dr ive io3 high during t cs . this will ensure that io3 / reset is not left floating or being pulled slowly to high by the internal or an external passive pull-up. thus, an unintended reset is not triggered by the io3 / reset# not being recognized as high before the end of t rp . the io3 / reset# signal is un used when the reset feature is disabled (cr2v[5]=0). the io3 / reset# signal has an internal pull-up resistor and may be left unconnected in the host system if not used for quad mode or the reset function. the internal pull-up will hold io3 / reset high after the host system has actively driven the signal high and then stops driving the signal. note that io3 / reset# cannot be shared by more than one spi-mio memory if any of them are operating in quad i/o mode as io3 being driven to or from one sele cted memory may look like a reset signal to a second non-selected memory sharing the same io3 / reset# signal. 3.9 voltage supply (v dd ) v dd is the voltage source for all devic e internal logic. it is the single voltage used for all device internal functions including read, program, and erase. 3.10 supply and signal ground (v ss ) v ss is the common voltage drain and ground reference fo r the device core, input signal receivers, and output drivers. 3.11 not connected (nc) no device internal signal is connected to the pack age connector nor is there any future plan to use the connector for a signal. the connection may safely be us ed for routing space for a signal on a printed circuit board (pcb).
november 6, 2013 s25fs-s_00_04 s25fs-s family 21 data sheet (preliminary) 3.12 reserved for future use (rfu) no device internal signal is currently connected to th e package connector but there is potential future use of the connector. it is recommended to not use rfu connectors for pcb r outing channels so that the pcb may take advantage of future enhanced features in compatible footprint devices. 3.13 do not use (dnu) a device internal signal may be connected to the package connector. the connection may be used by spansion for test or other purposes and is not inte nded for connection to any host system signal. any dnu signal related function will be inactive when the signal is at v il . the signal has an internal pull-down resistor and may be left unconn ected in the host system or may be tied to v ss . do not use these connections for pcb signal routing channels. do not connect any host system signal to these connections. 3.14 block diagrams figure 3.1 bus master and memory devices on t he spi bus - single bit data path s pi b us m as ter re s et# wp# s o s i s ck c s 2# c s 1# f s - s fl as h f s - s fl as h re s et# wp# s o s i s ck c s 2# c s 1#
22 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) figure 3.2 bus master and memory devices on the spi bus - dual bit data path figure 3.3 bus master and memory devices on the spi bus - quad bit data path s pi b us m as ter re s et# wp# io1 io0 s ck c s 2# c s 1# f s - s fl as h f s - s fl as h re s et# wp# io0 io1 s ck c s 2# c s 1# s pi b us m as ter io 3 / re s et# io2 io1 io0 s ck c s 1# f s - s fl as h re s et# / io 3 io2 io0 io1 s ck c s 1#
november 6, 2013 s25fs-s_00_04 s25fs-s family 23 data sheet (preliminary) 4. signal protocols 4.1 spi clock modes 4.1.1 single data rate (sdr) the s25fs-s family can be driven by an embedded microc ontroller (bus master) in either of the two following clocking modes. ? mode 0 with clock polarity (cpol) = 0 and, clock phase (cpha) = 0 ? mode 3 with cpol = 1 and, cpha = 1 for these two modes, input data into the device is always latched in on the rising edge of the sck signal and the output data is always available from the falling edge of the sck clock signal. the difference between the two modes is the clock polari ty when the bus master is in standby mode and not transferring any data. ? sck will stay at logic low state with cpol = 0, cpha = 0 ? sck will stay at logic high state with cpol = 1, cpha = 1 figure 4.1 spi sdr modes supported timing diagrams throughout the remainder of the docu ment are generally shown as both mode 0 and 3 by showing sck as both high and low at the fall of cs#. in some cases a timing diagram may show only mode 0 with sck low at the fall of cs#. in such a case, mode 0 timing simply means the clock is high at the fall of cs# so no sck rising edge set up or hold time to the falling edge of cs# is needed for mode 0. sck cycles are measured (counted) from one falling ed ge of sck to the next falling edge of sck. in mode 0 the beginning of the first sc k cycle in a command is measured from the falling edge of cs# to the first falling edge of sck because sck is already low at the beginning of a command. 4.1.2 double data rate (ddr) mode 0 and mode 3 are also supported for ddr comm ands. in ddr commands, the instruction bits are always latched on the rising edge of clock, the same as in sdr commands. however, the address and input data that follow the instruction are la tched on both the rising and falling edges of sck. the first address bit is latched on the first rising edge of sck following the falling edge at the end of the last instruction bit. the first bit of output data is driven on the falling edge at the end of the last access latency (dummy) cycle. sck cycles are measured (counted) in the same way as in sdr commands, from one falling edge of sck to the next falling edge of sck. in mode 0 the beginning of the first sck cycle in a command is measured from the falling edge of cs# to the first falling edge of sck because sck is already low at the beginning of a command. figure 4.2 spi ddr modes supported cpol=0_cpha=0_sclk cpol=1_cpha=1_sclk cs# si so msb msb cpol=0_cpha=0_sclk cpol=1_cpha=1_sclk cs# transfer_phase si so inst. 7 inst. 0 a31 a30 a0 m7 m6 m0 dlp7 dlp0 d0 d1 dummy / dlp address mode instruction
24 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 4.2 command protocol all communication between th e host system and s25fs-s family memory devices is in the form of units called commands. all commands begin with an 8-bit instruction that select s the type of information tr ansfer or device operation to be performed. commands may also have an address, in struction modifier, latency period, data transfer to the memory, or data transfer from the memory. all inst ruction, address, and data information is transferred sequentially between the host system and memory device. command protocols are also classified by a numerical nomenclature using three numbers to reference the transfer width of three command phases: ? instruction; ? address and instruction modifier (continuous read mode bits); ? data. single bit wide commands start with an instruction and ma y provide an address or data, all sent only on the si signal. data may be sent back to the host serially on the so signal. this is referenced as a 1-1-1 command protocol for single bit width instruction, singl e bit width address and modifier, single bit data. dual or quad input / output (i/o) commands provide an address sent from the host as bit pairs on io0 and io1 or, four bit (nibble) groups on io0, io1, io2, and io3. data is returned to the host similarly as bit pairs on io0 and io1 or, four bit (nibble) groups on io0, io1, io 2, and io3. this is referenced as 1-2-2 for dual i/o and 1-4-4 for quad i/o command protocols. the s25fs-s family also supports a qpi mode in which all information is transferred in 4-bit width, including the instruction, address, modifier, and data. th is is referenced as a 4-4-4 command protocol. commands are structured as follows: ? each command begins with cs# going low and ends with cs# returning high. the memory device is selected by the host driving the chip sele ct (cs#) signal low throughout a command. ? the serial clock (sck) marks the transfer of each bit or group of bits between the host and memory. ? each command begins with an 8-bit (byte) instruction. the instruction selects the type of information transfer or device operation to be performed. th e instruction transfers occur on sck rising edges. however, some read commands are modified by a prior read command, such that the instruction is implied from the earlier command. this is called continuou s read mode. when the device is in continuous read mode, the instruction bits are not transmitted at the beginning of the co mmand because the instruction is the same as the read command that initiated the continuous read mode. in continuous read mode the command will begin with the read address. thus, contin uous read mode removes eight instruction bits from each read command in a series of same type read commands. ? the instruction may be stand alone or may be followed by address bits to select a location within one of several address spaces in the device. the instruct ion determines the address space used. the address may be either a 24-bit or a 32-bit, byte boundary, a ddress. the address transfers occur on sck rising edge, in sdr commands, or on every sck edge, in ddr commands. ? in legacy spi mode, the width of all transfers follo wing the instruction are determined by the instruction sent. following transfers may continue to be single bit serial on only the si or serial output (so) signals, they may be done in two bit groups per (dual) transfer on the io0 and io1 signals, or they may be done in 4-bit groups per (quad) transfer on the io0-io3 signals. within the dual or quad gr oups the least significant bit is on io0. more significant bits are placed in significance order on each higher numbered io signal. single bits or parallel bit groups are transferred in most to least significant bit order. ? in qpi mode, the width of all transfers is a 4-bit wide (quad) transfer on the io0-io3 signals. ? dual and quad i/o read instructions send an instru ction modifier called continuous read mode bits, following the address, to indicate whether the next command will be of the same type with an implied, rather than an explicit, instruction. these mode bi ts initiate or end the continuous read mode. in continuous read mode, the next command thus does not provide an instruction byte, only a new address and mode bits. this reduces the time needed to send each command when the same command type is repeated in a sequence of comma nds. the mode bit transfers occur on sck rising edge, in sdr commands, or on every sck edge, in ddr commands.
november 6, 2013 s25fs-s_00_04 s25fs-s family 25 data sheet (preliminary) ? the address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before read data is returned to the host. ? write data bit transfers occur on sck rising edge, in sdr commands, or on every sck edge, in ddr commands. ? sck continues to toggle during any read access latency period. the latency may be zero to several sck cycles (also referred to as dummy cycles). at the end of the read latency cycles, the first read data bits are driven from the outputs on sck falling edge at the end of the last read latency cycle. the first read data bits are considered transferred to the host on the fo llowing sck rising edge. each following transfer occurs on the next sck rising edge, in sdr commands, or on every sck edge, in ddr commands. ? if the command returns read data to the host, the devi ce continues sending data transfers until the host takes the cs# signal high. the cs# signal can be driven high after any transfer in the read data sequence. this will terminate the command. ? at the end of a command that does not return data, the host drives the cs# input high. the cs# signal must go high after the eighth bit, of a stand alone inst ruction or, of the last write data byte that is transferred. that is, the cs# signal must be driven high when the number of bits after the cs# signal was driven low is an exact multiple of eight bits. if the cs # signal does not go high exactly at the eight bit boundary of the instruction or write data, the command is rejected and not executed. ? all instruction, address, and mode bits are shifted into the device with the most significant bits (msb) first. the data bits are shifted in and out of the device msb first. all data is transferred in byte units with the lowest address byte sent first. the following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments. ? all attempts to read the flash memory array duri ng a program, erase, or a write cycle (embedded operations) are ignored. the embedded operation will c ontinue to execute without any affect. a very limited set of commands are accepted during an embedded operation. these are discussed in the individual command descriptions. ? depending on the command, the time for execution varies. a command to read status information from an executing command is available to determine when the command completes execution and whether the command was successful. 4.2.1 command sequence examples figure 4.3 stand alone instruction command figure 4.4 single bit wide input command cs# sclk si so phase 7 6 5 4 3 2 1 0 instruction cs# sclk si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data
26 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) figure 4.5 single bit wide output command figure 4.6 single bit wide i/o command without latency figure 4.7 single bit wide i/o command with latency figure 4.8 dual i/o command figure 4.9 quad i/o command cs# sclk si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction data 1 data 2 cs# sclk si so phase 7 6 5 4 3 2 1 0 31 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address data 1 data 2 cs# sclk si so phase 7 6 5 4 3 2 1 0 31 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1 cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 30 2 0 6 4 2 0 6 4 2 0 6 4 2 0 31 3 1 7 5 3 1 7 5 3 1 7 5 3 1 instruction address mode dum data 1 data 2 cs# sclk io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 28 4 0 4 0 4 0 4 0 4 0 4 0 29 5 1 5 1 5 1 5 1 5 1 5 1 30 6 2 6 2 6 2 6 2 6 2 6 2 31 7 3 7 3 7 3 7 3 7 3 7 3 instruction address mode dummy d1 d2 d3 d4
november 6, 2013 s25fs-s_00_04 s25fs-s family 27 data sheet (preliminary) figure 4.10 quad i/o read command in qpi mode figure 4.11 ddr quad i/o read figure 4.12 ddr quad i/o read in qpi mode additional sequence diagrams, specific to each command, are provided in commands on page 85 cs# sclk io0 io1 io2 io3 phase 4 0 28 4 0 4 0 4 0 4 0 4 0 4 0 5 1 29 5 1 5 1 5 1 5 1 5 1 5 1 6 2 30 6 2 6 2 6 2 6 2 6 2 6 2 7 3 31 7 3 7 3 7 3 7 3 7 3 7 3 instruct. address mode dummy d1 d2 d3 d4 cs# sclk io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 28 24 20 16 12 8 4 0 4 0 7 6 5 4 3 2 1 0 4 0 4 0 29 25 21 17 13 9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1 30 26 22 18 14 10 6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2 31 27 23 19 15 11 7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3 instruction address mode dummy dlp d1 d2 cs# sclk io0 io1 io2 io3 phase 4 0 28 24 20 16 12 8 4 0 4 0 7 6 5 4 3 2 1 0 4 0 4 0 5 1 29 25 21 17 13 9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1 6 2 30 26 22 18 14 10 6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2 7 3 31 27 23 19 15 11 7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3 instruct. address mode dummy dlp d1 d2
28 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 4.3 interface states this section describes the input and output signal levels as related to the spi interface behavior. legend z = no driver - floating signal hl = host driving v il hh = host driving v ih hv = either hl or hh x = hl or hh or z ht = toggling between hl and hh ml = memory driving v il mh = memory driving v ih mv = either ml or mh 4.3.1 power-off when the core supply voltage is at or below the v dd (low) voltage, the device is co nsidered to be powered off. the device does not react to external signals, and is prevented from performing any program or erase operation. 4.3.2 low-power hardware data protection when v dd is less than v dd (cut-off) the memory device will ignore commands to ensure that program and erase operations can not start when the core supply voltage is out of the operating range. table 4.1 interface states summary interface state v dd sck cs# io3 / reset# wp# / io2 so / io1 si / io0 power-off november 6, 2013 s25fs-s_00_04 s25fs-s family 29 data sheet (preliminary) 4.3.3 power-on (cold) reset when the core voltage supply remains at or below the v dd (low) voltage for t pd time, then rises to v dd (minimum) the device will begin its power-on reset (por ) process. por continues until the end of t pu . during t pu the device does not react to external input signals nor drive any outputs. following the end of t pu the device transitions to the interface standby state and can accept commands. for additional information on por see power-on (cold) reset on page 38 4.3.4 hardware (warm) reset a configuration option is provided to allow io3 to be us ed as a hardware reset input when the device is not in quad mode or when it is in quad mode and cs# is high. when io3 / reset# is driven low for t rp time the device starts the hardware reset process. the process continues for t rph time. following the end of both t rph and the reset hold time foll owing the rise of reset# (t rh ) the device transitions to the interface standby state and can accept commands. for additional information on hardware reset see reset on page 38 4.3.5 interface standby when cs# is high the spi interface is in standby st ate. inputs other than reset# are ignored. the interface waits for the beginning of a new command. the next inte rface state is instruction cycle when cs# goes low to begin a new command. while in interface standby state the memory device draws standby current (i sb ) if no embedded algorithm is in progress. if an embedded algorithm is in progre ss, the related current is drawn until the end of the algorithm when the entire device returns to standby current draw. 4.3.6 instruction cy cle (legacy spi mode) when the host drives the msb of an instruction and cs# goes low, on the next rising edge of sck the device captures the msb of the in struction that begins the new command. on each following rising edge of sck the device captures the next lower significance bit of the 8-bi t instruction. the host keep s cs# low, and drives the write protect (wp#) an d io3/reset signals as needed for the instruction. ho wever, wp# is only relevant during instruction cycles of a wrr or wrar command and is otherwise ignored. io3/reset# is driven high when the device is not in quad mode (cr1v[1]=0) or qpi mode (cr2v[6]=0) and hardware reset is not required. each instruction selects the address space that is operated on and the transfer format used during the remainder of the command. the transfer format may be single, dual i/o, quad i/o, or ddr quad i/o. the expected next interface state depends on the instruction received. some commands are stand alone, needing no address or data transfer to or from the memory. the host returns cs# high after the rising edge of sck for the eight h bit of the instruction in such commands. the next interface state in this case is interface standby. 4.3.7 instruction cycle (qpi mode) in qpi mode, when cr2v[ 6]=1, instructions are transfe rred 4 bits per cycle. in this mode, instruction cycles are the same as a quad input cycle. see quad input cycle - host to memory transfer on page 30 . 4.3.8 single input cycle - host to memory transfer several commands transfer information a fter the instruction on the single seri al input (si) signal from host to the memory device. the host keeps reset# high, cs# lo w, and drives si as n eeded for the co mmand. the memory does not drive the serial output (so) signal. the expected next interface state depends on the instruct ion. some instructions continue sending address or data to the memory using additional single input cycles. ot hers may transition to single latency, or directly to single, dual, or quad output cycle states.
30 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 4.3.9 single latency (dummy) cycle read commands may have zero to seve ral latency cycles during which read data is read from the main flash memory array before transfer to the host. the numbe r of latency cycles are determined by the latency code in the configuration register (cr2 v[3:0]). during the la tency cycles, the host keeps reset# high, cs# low. the write protect (wp#) signal is ignored. the host ma y drive the si signal during these cycles or the host may leave si floating. the memory does not use any data driven on si / i/o0 or other i/o signals during the latency cycles. the memory does not drive the serial ou tput (so) or i/o signal s during the latency cycles. the next interface state dep ends on the command struct ure i.e. the numb er of latency cycl es, and whether the read is single, dual, or quad width. 4.3.10 single output cycle - memory to host transfer several commands transfer information back to the hos t on the single serial output (so) signal. the host keeps reset# high, cs# low. the write protect (wp#) signal is igno red. the memory ignores the serial input (si) signal. the me mory drives so with data. the next interface state continues to be single output cycle until the ho st returns cs# to high ending the command. 4.3.11 dual input cycle - host to memory transfer the read dual i/o command transfers two address or mode bits to the memory in each cycle. the host keeps reset# high, cs# low. the write protect (wp#) sig nal is ignored. the host drives address on si / io0 and so / io1. the next interface state following the de livery of address and mode bits is a dual latency cycle if there are latency cycles needed or dual output cycle if no latency is required. 4.3.12 dual latency (dummy) cycle read commands may have zero to seve ral latency cycles during which read data is read from the main flash memory array before transfer to the host. the numbe r of latency cycles are determined by the latency code in the configuration register (cr2 v[3:0]). during the la tency cycles, the host keeps reset# high, cs# low. the write protect (wp#) signal is ignored. the host may drive the si / io0 and so / io1 signals during these cycles or the host may leave si / io0 and so / io1 floating. the memory does not use any data driven on si / io0 and so / io1 during the la tency cycles. the host must stop dr iving si / io0 and so / io1 on the falling edge at the end of the last latency cycle. it is recommended that the host st op driving them during all latency cycles so that there is sufficie nt time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. th is prevents driver conflict between host and memory when the signal direction changes. the memory does not drive the si / io0 and so / io1 signals during the latency cycles. the next interface state follo wing the last latency cycle is a dual output cycle. 4.3.13 dual output cycle - memory to host transfer the read dual output and read dual i/o return data to the host two bits in each cycle. the host keeps reset# high, cs# low. the write protect (wp#) signal is ignored. the memory drives data on the si / io0 and so / io1 signals during the dual output cycles. the next interface state continues to be dual output cycle until the host returns cs# to high ending the command. 4.3.14 quad input cycle - host to memory transfer the quad i/o read command transfers four address or m ode bits to the memory in each cycle. in qpi mode the quad i/o read and page program commands transfer fo ur data bits to the memory in each cycle, including the instruction cycles. the host keeps cs# low, and drives the io signals. for quad i/o read the next interface state following the delivery of address and mode bits is a quad latency cycle if there are latency cycles needed or quad output cycle if no latency is required. for qpi mode page program, the host returns cs# high following the delivery of data to be programmed and the interface returns to standby state.
november 6, 2013 s25fs-s_00_04 s25fs-s family 31 data sheet (preliminary) 4.3.15 quad latency (dummy) cycle read commands may have zero to seve ral latency cycles during which read data is read from the main flash memory array before transfer to the host. the numbe r of latency cycles are determined by the latency code in the configuration register (cr2v[ 3:0]). during the latency cycles, the host keeps cs# low. the host may drive the io signals during these cycles or the host may leave the io floating. the memory does not use any data driven on io during the latency cycles. the host must stop driving the io signals on the falling edge at the end of the last latency cycle. it is recommended that the host stop driving them during all latency cycles so that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. this prevents driver conflict between host and memory when the signal direction changes. the memory does not dr ive the io sig nals during the latency cycles. the next interface state follo wing the last latency cycle is a quad output cycle. 4.3.16 quad output cycle - memory to host transfer the quad i/o read returns dat a to the host four bits in each cycle. the host keeps cs# low. the memory drives data on io0-io3 signals during the quad output cycles. the next interface state continues to be quad output cycle until the host returns cs# to high ending the command. 4.3.17 ddr quad input cycle - host to memory transfer the ddr quad i/o read command sends address, and mode bits to the memory on all the io signals. four bits are transferred on the ri sing edge of sck and four bits on the falling edge in each cycle. the host keeps cs# low. the next interface state following the delivery of address and mode bits is a ddr latency cycle. 4.3.18 ddr latency cycle ddr read commands may have one to several latency cycles during which read data is read from the main flash memory array before transfer to the host. the number of latency cycles are determined by the latency code in the configuration register (cr2v[3:0]). during the latency cycl es, the host keeps cs# low. the host may not drive the io signals during thes e cycles. so that there is sufficient time for the host drivers to turn off before the memory begins to drive. this prevents dr iver conflict between host and memory when the signal direction changes. the memory has an option to drive a ll the io signals with a data learning pattern (dlp) during the last 4 latency cycles. the dlp option should not be enabled when t here are fewer than five latency cycles so that there is at least one cycle of high impedance for turn around of t he io signals before the memory begins driving the dlp. when there are more th an 4 cycles of latency the memory does not drive the io signals until the last four cycles of latency. the next interface state following the last latency cycle is a ddr single, or quad output cycle, depending on the instruction. 4.3.19 ddr quad output cycle - memory to host transfer the ddr quad i/o read command returns bits to the host on all the io signals. four bits are transferred on the rising edge of sck and four bits on the falling edge in each cycle. the host keeps cs# low. the next interface state continues to be ddr quad output cycle until the host returns cs# to high ending the command. 4.4 configuration register effects on the interface the configuration register 2 volatile bits 3 to 0 ( cr2v[3:0]) select the variable latency for all array read commands except read and read sdfp (rsfdp). r ead always has zero latency cycles. rsfdp always has 8 latency cycles. the variable latency is also used in the otpr, and rdar commands. the configuration register bit 1 ( cr1v[1]) selects whether quad mode is enabled to switch wp# to io2 function, reset# to io3 function, and thus allow quad i/o read and qpi mode commands. quad mode must also be selected to allow ddr quad i/o read commands.
32 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 4.5 data protection some basic protection against unint ended changes to stored data are provided and controlled purely by the hardware design. these are described below. other software managed protection methods are discussed in the software section of this document. 4.5.1 power-up when the core supply voltage is at or below the v dd (low) voltage, the device is co nsidered to be powered off. the device does not react to external signals, and is prevented from performing any program or erase operation. program and erase operations continue to be prevented during the power-on reset (por) because no command is accepted until the exit from por to the interface standby state. 4.5.2 low power when v dd is less than v dd (cut-off) the memory device will ignore commands to ensure that program and erase operations can not start when the core supply voltage is out of the operating range. 4.5.3 clock pulse count the device verifies that all non-volatile memory and register data modifying commands consist of a clock pulse count that is a multiple of eight bit transfers (byte boundary) before executing them. a command not ending on an 8-bit (byte) boundary is ignored and no error status is set for the command.
november 6, 2013 s25fs-s_00_04 s25fs-s family 33 data sheet (preliminary) 5. electrical specifications 5.1 absolute maximum ratings notes: 1. see section 5.3.3, input signal overshoot on page 33 for allowed maximums during signal transition. 2. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 3. stresses above those listed under absolute maximum ratings may cause permanent damage to the de vice. this is a stress rating only; functional operation of the device at these or any other conditio ns above those indicated in the operational sections of this d ata sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 5.2 latch-up characteristics note: 1. excludes power supply v dd . test conditions: v dd = 1.8 v, one connection at a time tested, connections not being tested are at v ss . 5.3 operating ranges operating ranges define those limits between whic h the functionality of th e device is guaranteed. 5.3.1 power supply voltages v dd ????????????.......... .............. ....... 1.7v to 2.0v 5.3.2 temperature ranges industrial (i) devices ambient temperature (t a )............. .............. ............ ?40c to +85c automotive (a) info tainment devices ambient temperature (t a )............. .............. ............ ?40c to +105c automotive operating and performance parameters wil l be determined by device characterization and may vary from standard industrial temperature range devi ces as currently shown in this specification. 5.3.3 input si gnal overshoot during dc conditions, input or i/o signals should remain equal to or between v ss and v dd . during voltage transitions, inputs or i/os may overshoot v ss to -1.0v or overshoot to v dd +1.0v, for periods up to 20 ns. table 5.1 absolute maximum ratings storage temperature plastic packages ?65 c to +150 c ambient temperature with power applied ?65 c to +125 c v dd ?0.5 v to +2.5v input voltage with respect to ground (v ss ) (note 1) ?0.5 v to v dd + 0.5v output short circuit current (note 2) 100 ma table 5.2 latch-up specification description min max unit input voltage with respect to v ss on all input only connections -1.0 v dd + 1.0 v input voltage with respect to v ss on all i/o connections -1.0 v dd + 1.0 v v dd current -100 +100 ma
34 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) figure 5.1 maximum negative overshoot waveform figure 5.2 maximum positive overshoot waveform 5.4 power-up and power-down the device must not be selected at power-up or power-dow n (that is, cs# must follow the voltage applied on v dd ) until v dd reaches the correct value as follows: ? v dd (min) at power-up, and then for a further delay of t pu ? v ss at power-down a simple pull-up resistor on chip select (cs#) can usually be used to insure safe and proper power-up and power-down. the device ignores all instructions until a time delay of t pu has elapsed after the moment that v dd rises above the minimum v dd threshold (see figure 5.3 ). however, correct operation of the device is not guaranteed if v dd returns below v dd (min) during t pu . no command should be sent to the device until the end of t pu . the device draws i por during t pu . after power-up (t pu ), the device is in standby mode, draws cmos standby current (i sb ), and the wel bit is reset. during power-down or voltage drops below v dd (cut-off), the voltage must drop below v dd (low) for a period of t pd for the part to initialize correctly on power-up. see figure 5.4 . if during a voltage drop the v dd stays above v dd (cut-off) the part will stay initializ ed and will work correctly when v dd is again above v dd (min). in the event power-on reset (por) did not complete corre ctly after power-up, the assertion of the reset# signal or receiving a software reset command (reset) will restart the por process. normal precautions must be taken for su pply rail decoupling to stabilize the v dd supply at the device. each device in a system should have the v dd rail decoupled by a suitable capacitor close to the package supply connection (this capacitor is gener ally of the order of 0.1 f). v ss to v dd - 1.0v 20 n s v dd + 1.0v 20 n s v ss to v dd table 5.3 fs-s power-up / power-down voltage and timing symbol parameter min max unit v dd (min) v dd (minimum operation voltage) 1.7 v v dd (cut-off) v dd (cut 0ff where re-initialization is needed) 1.5 v v dd (low) v dd (low voltage for initialization to occur) 0.7 v t pu v dd (min) to read operation 300 s t pd v dd (low) time 10.0 s
november 6, 2013 s25fs-s_00_04 s25fs-s family 35 data sheet (preliminary) figure 5.3 power-up figure 5.4 power-down and voltage drop tpu f u ll device acce ss v dd (min) v dd (m a x) time v dd (m a x) v dd (min) v dd (c u t-off) v dd (low) tpu device acce ss allowed no device acce ss allowed tpd time
36 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 5.5 dc characteristics applicable within operating ranges. notes: 1. typical values are at t ai = 25 c and v dd = 1.8v. 2. outputs unconnected during read data return. output switching current is not included. 5.5.1 active power and standby power modes the device is enabled and in the active power mode when chip select (cs#) is low. when cs# is high, the device is disabled, but may still be in an active power mode until all program, er ase, and write operations have completed. the device then goes into the stand by power mode, and power consumption drops to i sb . table 5.4 fs-s dc characteristics symbol parameter test conditions min typ (1) max unit v il input low voltage -0.5 0.3xv dd v v ih input high voltage 0.7xv dd v dd +0.4 v v ol output low voltage i ol = 0.1 ma 0.2 v v oh output high voltage i oh = ?0.1 ma v dd - 0.2 v i li input leakage current v dd = v dd max, v in = v ih or v ss , cs# = v ih 2 a i lo output leakage current v dd = v dd max, v in = v ih or v ss , cs# = v ih 2 a i cc1 active power supply current (read) (2) serial sdr@50 mhz serial sdr@133 mhz quad sdr@133 mhz quad ddr@80 mhz 10 20 60 70 18 30 65 90 ma i cc2 active power supply current (page program) cs# = v dd 60 100 ma i cc3 active power supply current (wrr or wrar) cs# = v dd 60 100 ma i cc4 active power supply current (se) cs# = v dd 60 100 ma i cc5 active power supply current (be) cs# = v dd 60 100 ma i sb (industrial) standby current io3/reset#, cs# = v dd ; si, sck = v dd or v ss , industrial temp 70 100 a i sb (automotive) standby current io3/reset#, cs# = v dd ; si, sck = v dd or v ss , automotive temp 70 300 a i por power-on reset current io3/reset#, cs# = v dd ; si, sck = v dd or v ss 80 ma
november 6, 2013 s25fs-s_00_04 s25fs-s family 37 data sheet (preliminary) 6. timing specifications 6.1 key to switching waveforms figure 6.1 waveform element meanings 6.2 ac test conditions figure 6.2 test setup notes: 1. input slew rate measured from input pulse min to max at v dd max. example: (1.9v x 0.8) - (1.9v x 0.2) = 1.14v; 1.14v/1.25v/ns = 0.9 ns rise or fall time. 2. ac characteristics tables assume clock and data signals have the same slew rate (slope). figure 6.3 input, output, and timing reference levels input symbol output valid at logic high or low high impedance any change permitted logic high logic low high impedance changing, state unknown logic high logic low valid at logic high or low table 6.1 ac measurement conditions symbol parameter min max unit c l load capacitance 30 pf input pulse voltage 0.2xv dd 0.8 v dd v input slew rate 0.23 1.25 v/ns input rise and fall times 0.9 5 ns input timing ref voltage 0.5 v dd v output timing ref voltage 0.5 v dd v device under te s t c l v dd + 0.4v 0.7 x v dd 0. 3 x v dd - 0.5v timing reference level 0.5 x v dd v dd - 0.2v 0.2v inp u t level s o u tp u t level s
38 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 6.2.1 capacitance characteristics note: 1. parameter values are not 100% tested. for more details, please refer to the ibis models. 6.3 reset 6.3.1 power-on (cold) reset the device executes a power-on reset (por) process until a time delay of t pu has elapsed after the moment that v dd rises above the minimum v dd threshold. see figure 5.3 on page 35 , table 5.3 on page 34 . the device must not be selected (cs# to go high with v dd ) during power-up (t pu ), i.e. no commands may be sent to the device until the end of t pu . the io3 / reset# signal functions as the reset# input when cs# is high for more than t cs time or when quad mode is not enabled cr1v[1]=0. reset# is ignored during por. if reset# is low during por and remains low through and beyond the end of t pu , cs# must remain high until t rh after reset# returns high. reset# must return hi gh for greater than t rs before returning low to initiate a hardware reset. figure 6.4 reset low at the end of por figure 6.5 reset high at the end of por figure 6.6 por followed by hardware reset table 6.2 capacitance parameter test conditions min max unit c in input capacitance (applies to sck, cs#, io3/reset#) 1 mhz 8 pf c out output capacitance (applies to all i/o) 1 mhz 8 pf vcc reset# cs# if reset# is low at tpu end cs# must be high at tpu end tpu trh vcc reset# cs# if reset# is high at tpu end cs# may stay high or go low at tpu end tpu tpu vcc reset# cs# trs tpu tpu
november 6, 2013 s25fs-s_00_04 s25fs-s family 39 data sheet (preliminary) 6.3.2 io3 / reset# input init iated hardware (warm) reset the io3 / reset# signal functions as the reset# input when cs# is high for more than t cs time or when quad mode is not enabled cr1v[1]=0. the io3 / reset# input has an internal pull-up to v dd and may be left unconnected if quad mode is not used. the t cs delay after cs# goes high gives the memory or host system time to drive io3 high after its use as a quad mo de i/o signal while cs# was low. the inte rnal pull-up to v dd will then hold io3 / reset# high until the ho st system begins driv ing io3 / reset#. the io3 / reset# input is i gnored while cs# remains high during t cs , to avoid an unintended reset operation. if cs# is driven low to st art a new command, io3 / reset# is used as io3. when the device is not in quad mode or, when cs# is high, and io3 / reset# transitions from v ih to v il for > t rp , following t cs , the device will reset register states in the same manner as power-on reset but, does not go through the full reset process that is perform ed during por. the hardware reset process requires a period of t rph to complete. if the por process did not comp lete correctly for any reason during power-up (t pu ), reset# going low will initiate the full por process instead of the hardware reset process and will require t pu to complete the por process. the reset command is independent of the state of io 3 / reset#. if io3 / reset# is high or unconnected, and the reset instruction is issued, the device will perform software reset. additional io3 reset# notes: ? io3 / reset# must be high for t rs following t pu or t rph , before going low again to initiate a hardware reset. ? when io3 / reset# is driven low for at least a minimum period of time (t rp ), following t cs , the device terminates any operation in progress, makes all out puts high impedance, and ignores all read/write commands for the duration of t rph . the device resets the interface to standby state. ? if quad mode and the io3 / reset# feature are enable d, the host system should not drive io3 low during t cs, to avoid driver contention on io3. immediately foll owing commands that transfer data to the host in quad mode, e.g. quad i/o read, the memory drives io3 / reset high during t cs, to avoid an unintended reset operation. immediately following commands that transfer data to the memory in quad mode, e.g. page program, the host system should drive io3 / reset high during t cs, to avoid an unintended reset operation. ? if quad mode is not enabled, and if cs# is low at t he time io3 / reset# is asserted low, cs# must return high during t rph before it can be asserted low again after t rh . notes: 1. io3 / reset# low is ignored during power-up (t pu ). if reset# is asserted during the end of t pu , the device will remain in the reset state and t rh will determine when cs# may go low. 2. if quad mode is enabled, io3 / reset# low is ignored during t cs . 3. sum of t rp and t rh must be equal to or greater than t rph . figure 6.7 hardware reset when quad mode is not enabled and io3 / reset# is enabled table 6.3 hardware reset parameters parameter description limit time unit t rs reset setup - prior reset end and reset# high before reset# low min 50 ns t rph reset pulse hold - reset# low to cs# low min 35 s t rp reset# pulse width min 200 ns t rh reset hold - reset# high before cs# low min 50 ns io3_reset# cs# any prior reset trs trp trh trh trph trph
40 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) figure 6.8 hardware reset when quad mode and io3 / reset# are enabled 6.4 sdr ac characteristics notes: 1. only applicable as a constraint for wrr or wrar instruction when srwd is set to a 1. 2. full v dd range and cl=30 pf. 3. full v dd range and cl=15 pf. 4. output high-z is defined as the point where data is no longer driven. 5. t cs and t dis require additional time when the reset feature and quad mode are enabled (cr2v[5]=1 and cr1v[1]=1). io3_reset# cs# reset pulse prior access using io3 for data trp trh trph tc s tdis table 6.4 ac characteristics symbol parameter min typ max unit f sck, r sck clock frequency for read and 4read instructions dc 50 mhz f sck, c sck clock frequency for fast_read, 4fast_read, and the following dual and quad commands: qor, 4qor, dior, 4dior, qior, 4qior dc 133 mhz f sck, d sck clock frequency for the following ddr commands: qior, 4qior dc 80 mhz p sck sck clock period 1/ f sck t wh , t ch clock high time 50% p sck -5% 50% p sck +5% ns t wl , t cl clock low time 50% p sck -5% 50% p sck +5% ns t crt , t clch clock rise time (slew rate) 0.1 v/ns t cft , t chcl clock fall time (slew rate) 0.1 v/ns t cs cs# high time (read instructions) cs# high time (read instructions when reset feature and quad mode are both enabled) cs# high time (program/erase instructions) 10 20 (5) 50 ns t css cs# active setup time (relative to sck) 2 ns t csh cs# active hold time (relative to sck) 3 ns t su data in setup time 2 ns t hd data in hold time 3 ns t v clock low to output valid 8 (2) 6 (3) ns t ho output hold time 1 ns t dis output disable time (4) output disable time (when reset feature and quad mode are both enabled) 8 20 (5) ns t wps wp# setup time (1) 20 ns t wph wp# hold time (1) 100 ns
november 6, 2013 s25fs-s_00_04 s25fs-s family 41 data sheet (preliminary) 6.4.1 clock timing figure 6.9 clock timing 6.4.2 input / output timing figure 6.10 spi single bit input timing figure 6.11 spi single bit output timing figure 6.12 spi sdr mio timing v il m a x v ih min tch tcrt tcft tcl v dd / 2 p s ck cs# sck si so msb in lsb in tcss tcss tcsh tcsh tcs tsu thd cs# sck si so msb out lsb out tcs tho tv tdis cs# sclk io msb in lsb in msb out lsb out tcsh tcsh tcss tcss tsu thd tho tcs tdis tv tv
42 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) figure 6.13 wp# input timing 6.5 ddr ac characteristics . notes: 1. cl=15 pf. 2. output slew rate is measured between 20% and 80% of v dd . cs# wp# sclk si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 wrr or wrar instruction input data twps twph table 6.5 ac characteristics 80 mhz operation symbol parameter min typ max unit f sck, r sck clock frequency for ddr read instruction dc 80 mhz p sck, r sck clock period for ddr read instruction 12.5 ns t crt clock rise time (slew rate) 1.5 v/ns t cft clock fall time (slew rate) 1.5 v/ns t wh , t ch clock high time 50% p sck -5% 50% p sck +5% ns t wl , t cl clock low time 50% p sck -5% 50% p sck +5% ns t cs cs# high time (read instructions) cs# high time (read instructions when reset feature is enabled) 10 20 ns t css cs# active setup time (relative to sck) 2 ns t csh cs# active hold time (relative to sck) 3 ns t su io in setup time 1.5 ns t hd io in hold time 1.5 ns t v clock low to output valid 1.5 6 (1) ns t ho output hold time 1.5 ns t dis output disable time output disable time (when reset feature is enabled) 8 20 ns t ihtu time uncertainty due to variation in v ih 130 ps t iltu time uncertainty due to variation in v il 130 ps t io_skew first io to last io data valid time 400 ps t iort output rise time given 1.8v swing and 2.0v/ns slew 1.5 ns t ioft output fall time given 1.8v swing and 2.0v/ns slew 1.5 ns t v clock to data valid jitter 80 ps
november 6, 2013 s25fs-s_00_04 s25fs-s family 43 data sheet (preliminary) 6.5.1 ddr input timing figure 6.14 spi ddr input timing 6.5.2 ddr output timing figure 6.15 spi ddr output timing figure 6.16 spi ddr data valid window 1. data valid calculation at 80 mhz: t dv = t ch (min) ? t iort ? t io_skew ? t ihtu - t v t dv = 5.62 ns ? 1.5 ns ? 400 ps ? 130 ps ? 80 ps t dv = 3.51 ns (56% of the total half clock in the worst case scenario) c s # s ck s i_or_io s o m s b in l s b in tc ss tc ss tc s h tc s h tc s t s u t s u thd thd cs# sck si so_or_io msb lsb tcs tho tv tv tdis sck io0 io1 io2 io3 io_valid slow d1 . slow d2 fast d1 fast d2 d1 d2 tv tv tv tv tio_skew tdv tcl tcl tch tiort_or_tioft tihtu tiltu
44 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 7. physical interface 7.1 soic 16-lead package 7.1.1 soic 16 connection diagram figure 7.1 16-lead soic package (so3016), top view note: 1. the reset# input has an internal pull-up and may be left unconnected in the system if quad mode and hardware reset are not in use. 1 2 3 4 16 15 14 1 3 io 3 /re s et# vdd rfu nc dnu rfu s i/io0 s ck 5 6 7 8 12 11 10 9 wp#/io2 v ss dnu dnu nc rfu c s # s o/io1
november 6, 2013 s25fs-s_00_04 s25fs-s family 45 data sheet (preliminary) 7.1.2 soic 16 physical diagram figure 7.2 soic 16-lead, 300-mil body width (so3016)
46 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 7.2 8-connector packages 7.2.1 8-connector diagrams figure 7.3 8-pin plastic small outline package (soic8) figure 7.4 8-connector package (wson 6x5), top view note: 1. the reset# input has an internal pull-up and may be left unconnected in the system if quad mode and hardware reset are not in use. 1 2 3 4 8 7 6 5 c s # s o / io1 wp# / io2 v ss s i / io0 s ck io 3 / re s et# vdd s oic 1 2 3 4 5 6 7 8 cs# so/io1 io3/reset# sck si/io0 wson wp#/io2 vdd vss
november 6, 2013 s25fs-s_00_04 s25fs-s family 47 data sheet (preliminary) 7.2.2 8-connector physical diagrams figure 7.5 soic 8-lead, 208 mil body width (soc008) 3 602 \ 16-0 38 .0 3 \ 9.1.6 note s : 1. all dimen s ion s are in both inche s and millmeter s . 2. dimen s ioning and tolerancing per a s me y14.5m - 1994. 3 . dimen s ion d doe s not include mold fla s h, protru s ion s or gate burr s . mold fla s h, protru s ion s or gate burr s s hall not exceed 0.15 mm per end. dimen s ion e1 doe s not include interlead fla s h or protru s ion interlead fla s h or protru s ion s hall not exceed 0.25 mm per s ide. d and e1 dimen s ion s are determined at datum h. 4. the package top may be s maller than the package bottom. dimen s ion s d and e1 are determined at the outmo s t extreme s of the pla s tic body exclu s ive of mold fla s h, tie bar burr s , gate burr s and interlead fla s h. but including any mi s match between the top and bottom of the pla s tic body. 5. datum s a and b to be determined at datum h. 6. "n" i s the maximum number of terminal po s ition s for the s pecified package length. 7. the dimen s ion s apply to the flat s ection of the lead between 0.10 to 0.25 mm from the lead tip. 8 . dimen s ion " b " doe s not include dambar protru s ion. allowable dambar protru s ion s hall be 0.10 mm total in exce ss of the " b " dimen s ion at maximum material condition. the dambar cannot be located on the lower radiu s of the lead foot. 9. thi s chamfer feature i s optional. if it i s not pre s ent, then a pin 1 identifier mu s t be located within the index area indicated. 10. lead coplanarity s hall be within 0.10 mm a s mea s ured from the s eating plane. package s oc 00 8 (inche s ) s oc 00 8 (mm) jedec s ymbol min max min max a 0.069 0.0 8 5 1.75 3 2.159 a1 0.002 0.009 8 0.051 0.249 a2 0.067 0.075 1.70 1.91 b 0.014 0.019 0. 3 56 0.4 83 b 1 0.01 3 0.01 8 0. 33 0 0.457 c 0.0075 0.0095 0.191 0.241 c1 0.006 0.00 8 0.152 0.20 3 d 0.20 8 b s c 5.2 83 b s c e 0. 3 15 b s c 8 .001 b s c e1 0.20 8 b s c 5.2 83 b s c e .050 b s c 1.27 b s c l 0.020 0.0 3 0 0.50 8 0.762 l1 .049 ref 1.25 ref l2 .010 b s c 0.25 b s c n 8 8 0? 8 ?0? 8 ? 1 5? 15? 5? 15? 2 0? 0?
48 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) figure 7.6 wson 8-contact 6x5 mm leadless (wnd008) g1071 \ 16-038.30 \ 02.22.12 notes: 1. dimensioning and tolerancing conforms to asme y14.5m - 1994. 2. all dimensions are in millmeters. 3. n is the total number of terminals. 4 dimension ?b? applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension ?b? should not be measured in that radius area. 5 nd refers to the number of terminals on d side. 6. max. package warpage is 0.05mm. 7. maximum allowable burr is 0.076mm in all directions. 8 pin #1 id on top will be laser marked. 9 bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. symbol min nom max notes e 1.27 bsc. n 8 3 nd 4 5 l 0.55 0.60 0.65 b 0.35 0.40 0.45 4 d2 3.90 4.00 4.10 e2 3.30 3.40 3.50 d 5.00 bsc e 6.00 bsc a 0.70 0.75 0.80 a1 0.00 0.02 0.05 k 0.20 min. package wnd008
november 6, 2013 s25fs-s_00_04 s25fs-s family 49 data sheet (preliminary) figure 7.7 wson 8-contact 6x8 mm leadless (wnh008) g1021 \ 16-038.30 \ 10.28.11 notes: 1. dimensioning and tolerancing conforms to asme y14.5m - 1994. 2. all dimensions are in millmeters. 3. n is the total number of terminals. 4 dimension ?b? applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension ?b? should not be measured in that radius area. 5 nd refers to the number of terminals on d side. 6. max. package warpage is 0.05mm. 7. maximum allowable burrs is 0.076mm in all directions. 8 pin #1 id on top will be laser marked. 9 bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. symbol min nom max note e 1.27 bsc. n 8 3 nd 4 5 l 0.45 0.50 0.55 b 0.35 0.40 0.45 4 d2 3.90 4.00 4.10 e2 3.30 3.40 3.50 d 6.00 bsc e 8.00 bsc a 0.70 0.75 0.80 a1 0.00 --- 0.05 k 0.20 min. package wnh008
50 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 7.3 fab024 24-ball bga package 7.3.1 connection diagrams figure 7.8 24-ball bga, 5x5 ball foot print (fab024), top view notes: 1. signal connections are in the same relative positions as fa c024 bga, allowing a single pcb footprint to use either package. 2. the reset# input has an internal pull-up and may be left unconnected in the system if quad mode and hardware reset are not in use. 3 25 4 1 nc nc nc rfu b d e a c vss sck nc vdd dnu rfu cs# nc wp#/io2 dnu si/io0 so/io1 nc io3/ reset# dnu nc nc nc rfu nc
november 6, 2013 s25fs-s_00_04 s25fs-s family 51 data sheet (preliminary) 7.3.2 physical diagram figure 7.9 ball grid array 24-ball 6x8 mm (fab024)
52 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 7.4 fac024 24-ball bga package 7.4.1 connection diagram figure 7.10 24-ball bga, 4x6 ball footprint (fac024), top view notes: 1. signal connections are in the same relative positions as fab0 24 bga, allowing a single pcb footprint to use either package. 2. the reset# input has an internal pull-up and may be left unconnected in the system if quad mode and hardware reset are not in use. 3 24 1 nc nc rfu b d e a c vss sck vdd dnu rfu cs# wp#/io2 dnu si/io0 so/io1 io3/ reset# dnu nc nc rfu nc nc nc nc nc nc f
november 6, 2013 s25fs-s_00_04 s25fs-s family 53 data sheet (preliminary) 7.4.2 physical diagram figure 7.11 ball grid array 24-ball 6 x 8 mm (fac024) 7.4.3 special handling instru ctions for fbga packages flash memory devices in bga packages may be damage d if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if t he package body is exposed to temperatures above 150c for prolonged periods of time. package fac024 jedec n/a d x e 8.00 mm x 6.00 mm nom package symbol min nom max note a --- --- 1.20 profile a1 0.25 --- --- ball height a2 0.70 --- 0.90 body thickness d 8.00 bsc. body size e 6.00 bsc. body size d1 5.00 bsc. matrix footprint e1 3.00 bsc. matrix footprint md 6 matrix size d direction me 4 matrix size e direction n 24 ball count ? b 0.35 0.40 0.45 ball diameter e 1.00 bsc. ball pitchl sd/ se 0.5/0.5 solder ball placement depopulated solder balls j package outline type 3642 f16-038.9 \ 09.10.09 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populated solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. datum c is the seating plane and is defined by the crowns of the solder balls. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 10 outline and dimensions per customer requirement.
54 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) software interface this section discusses the features and behaviors most re levant to host system software that interacts with s25fs-s family memory devices. 8. address space maps 8.1 overview 8.1.1 extended address the s25fs-s family supports 32-bit (4-byte) addresse s to enable higher density devices than allowed by previous generation (legacy) spi devices that supporte d only 24-bit (3-byte) addresses. a 24-bit, byte resolution, address can access only 16-mbytes (128-mbits) maximum densi ty. a 32-bit, by te resolution, address allows direct addressing of up to a 4-gbytes (32-gbits) address space. legacy commands continue to support 24-bit addresses for backward software compatibility. extended 32-bit addresses are enabled in two ways: ? extended address mode ? a volatile configuration r egister bit that changes all legacy commands to expect 32 bits of address supplied from the host system. ? 4-byte address commands ? that perform both legacy and new functions, which always expect 32-bit address. the default condition for extended address mode, after power-up or reset, is controlled by a non-volatile configuration bit. the default extended address mode ma y be set for 24- or 32-bit addresses. this enables legacy software compatible ac cess to the first 128 mbits of a device or for the device to start directly in 32-bit address mode. the 128-mbit density member of the s25fs-s family supports the extended address features in the same way but in essence ignores bits 31 to 24 of any address because the main flash array only needs 24 bits of address. this enables simple migration from the 128-m b density to higher density devices without changing the address handling aspects of software. 8.1.2 multiple address spaces many commands operate on the main flash memory array. some commands operate on address spaces separate from the main flash array. each separate addr ess space uses the full 24- or 32-bit address but may only define a small portion of the available address space. 8.2 flash memory array the main flash array is divided into erase units called physical sectors. the fs-s family physical sectors may be configured as a hybrid combination of eight 4-kb parameter sectors at the top or bottom of the addr ess space with all but one of the remaining sectors being uniform size. because the group of eight 4-kb parameter sectors is in total smaller than a uniform sector, the group of 4-kb physical sectors respectively overlay (replace) the top or bottom 32 kb of the highest or lowest address uniform sector. the parameter sector erase commands (20h or 21h) mu st be used to erase the 4-kb sectors individually. the sector (uniform block) erase commands (d8h or dch) must be used to erase any of the remaining sectors, including the portion of highest or lowest addre ss sector that is not overlaid by the parameter sectors. the uniform block erase command has no effect on parameter sectors. configuration register 1 non-volatile bit 2 (cr1nv[2 ]) equal to 0 overlays the parameter sectors at the bottom of the lowest address uniform sector. cr1nv[2] = 1 overlays the par ameter sectors at the top of the highest address uniform sector. see section 8.6, registers on page 59 for more information. there is also a configuration option to remove the 4- kb parameter sectors from the address map so that all sectors are uniform size. configuration register 3 volatile bit 3 (cr3v[3]) equal to 0 selects the hybrid sector
november 6, 2013 s25fs-s_00_04 s25fs-s family 55 data sheet (preliminary) architecture with 4-kb parameter se ctors. cr3v[3]=1 select s the uniform sector architecture without parameter sectors. uniform physical se ctors are 64 kb in fs128s and fs256s. both devices also may be configured to use the sect or (uniform block) erase commands to erase 256-kb logical blocks rather than individual 64-kb physical se ctors. this configuration option (cr3v[1]=1) allows lower density devices to emulate the same sector er ase behavior as higher density members of the family that use 256-kb physical sectors. th is can simplify software migration to the higher density members of the family. table 8.1 s25fs256s sector address map, bottom 4-kb sectors, 64-kb physi cal uniform sectors sector size (kbyte) sector count sector range address range (byte address) notes 4 8 sa00 00000000h-00000fffh sector starting address ? sector ending address : : sa07 00007000h-00007fffh 32 1 sa08 00008000h-0000ffffh 64 511 sa09 00010000h-0001ffffh : : sa519 01ff0000h-01ffffffh table 8.2 s25fs256s sector address map, top 4-kb sectors, 64-kb physical uniform sectors sector size (kbyte) sector count sector range address range (byte address) notes 64 511 sa00 0000000h-000ffffh sector starting address ? sector ending address :: sa510 01fe0000h-01feffffh 32 1 sa511 01ff0000h-01ff7fffh 48 sa512 01ff8000h-01ff8fffh :: sa519 01fff000h-01ffffffh table 8.3 s25fs256s sector address map, uniform 64-kb physical sectors sector size (kbyte) sector count sector range address range (8-bit) notes 64 512 sa00 0000000h-000ffffh sector starting address ? sector ending address : : sa511 1ff0000h-1ffffffh table 8.4 s25fs256s sector address map, bottom 4-kb sectors, 256-kb logical uniform sectors sector size (kbyte) sector count sector range address range (byte address) notes 4 8 sa00 00000000h-00000fffh sector starting address ? sector ending address : : sa07 00007000h-00007fffh 224 1 sa08 00008000h-0003ffffh 256 127 sa09 00040000h-0007ffffh : : sa135 01fc0000h-01ffffffh
56 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) table 8.5 s25fs256s sector address map, top 4-kb sectors, 256-kb logical uniform sectors sector size (kbyte) sector count sector range address range (byte address) notes 256 127 sa00 0000000h-003ffffh sector starting address ? sector ending address :: sa126 01f80000h-01fbffffh 224 1 sa127 01fc0000h-01fc7fffh 48 sa128 01ff8000h-01ff8fffh :: sa135 01fff000h-01ffffffh table 8.6 s25fs256s sector address map, uniform 256-kb logical sectors sector size (kbyte) sector count sector range address range (8-bit) notes 256 128 sa00 00000000h-0003ffffh sector starting address ? sector ending address : : sa127 01fc0000h-01ffffffh table 8.7 s25fs128s sector and memory addr ess map, bottom 4-kb sectors sector size (kbyte) sector count sector range address range (byte address) notes 4 8 sa00 00000000h-00000fffh sector starting address ? sector ending address : : sa07 00007000h-00007fffh 32 1 sa08 00008000h-0000ffffh 64 255 sa09 00010000h-0001ffffh : : sa263 00ff0000h-00ffffffh table 8.8 s25fs128s sector and memory a ddress map, top 4-kb sectors sector size (kbyte) sector count sector range address range (byte address) notes 64 255 sa00 0000000h-000ffffh sector starting address ? sector ending address : : sa254 00fe0000h-00feffffh 32 1 sa255 00ff0000h - 00ff7fffh 4 8 sa256 00ff8000h - 00ff8fffh : : sa263 00fff000h-00ffffffh table 8.9 s25fs128s sector and memory ad dress map, uniform 64-kb blocks sector size (kbyte) sector count sector range address range (byte address) notes 64 256 sa00 0000000h-0000ffffh, sector starting address ? sector ending address : : sa255 00ff0000h-0ffffffh
november 6, 2013 s25fs-s_00_04 s25fs-s family 57 data sheet (preliminary) note : these are condensed tables that use a couple of sectors as refe rences. there are address ranges that are not explicitly listed. all 4-kb sectors have the pattern xxxx000h-xxxxfffh. all 64-kb sectors have the pattern xxx0000h-xxxffffh. all 256-kb sectors have the pattern xx00000h-xx3ffffh, xx40000h- xx7ffffh, xx80000h-xxcffff h, or xxd0000h-xxfffffh. 8.3 id-cfi address space the rdid command (9fh) reads information from a separate flash memory address space for device identification (id) and common flash interface (cfi) information. see section 12.4, device id and common flash interface (id-cfi) address map on page 143 for the tables defining the contents of the id-cfi address space. the id-cfi addr ess space is programmed by spansion and read-only for the host system. 8.4 jedec jesd216 serial flash disco verable parameters (sfdp) space. the rsfdp command (5ah) reads information from a separate flash memory address space for device identification, feature, and configuration information, in accord with the jedec jesd216 standard for serial flash discoverable parameters. the id-cfi address spac e is incorporated as one of the sfdp parameters. see section 12.3, serial flash discoverable para meters (sfdp) address map on page 142 for the tables defining the contents of the sfdp address space. th e sfdp address space is programmed by spansion and read-only for the host system. table 8.10 s25fs128s sector address map, bottom 4-kb sectors, 256- kb logical uniform sectors sector size (kbyte) sector count sector range address range (byte address) notes 4 8 sa00 00000000h-00000fffh sector starting address ? sector ending address : : sa07 00007000h-00007fffh 224 1 sa08 00008000h-0003ffffh 256 63 sa09 00040000h-0007ffffh : : sa71 00fc0000h-00ffffffh table 8.11 s25fs128s sector address map, top 4-kb sectors, 256-kb logical uniform sectors sector size (kbyte) sector count sector range address range (byte address) notes 256 63 sa00 00000000h-0003ffffh sector starting address ? sector ending address :: sa62 00f80000h-00fbffffh 224 1 sa63 00fc0000h-00ff7fffh 48 sa64 00ff8000h-00ff8fffh :: sa71 00fff000h-00ffffffh table 8.12 s25fs128s sector and memory addr ess map, uniform 256-kb blocks sector size (kbyte) sector count sector range address range (byte address) notes 256 64 sa00 00000000h-0003ffffh sector starting address ? sector ending address : : sa63 00fc0000h-00ffffffh
58 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 8.5 otp address space each fs-s family memory device has a 1024-byte one- time program (otp) address space that is separate from the main flash array. the otp area is divided in to 32, individually lockable, 32-byte aligned and length regions. in the 32-byte region starting at address zero: ? the 16 lowest address bytes are programmed by span sion with a 128-bit random number. only spansion is able to program zeros in these bytes. programmin g ones in these byte loca tions is ignored and does not affect the value programmed by spansion. attempting to program any zero in these byte locations will fail and set p_err. ? the next 4 higher address bytes (otp lock bytes) are used to provide one bit per otp region to permanently protect each region from programming. the bytes are er ased when shipped from spansion. after an otp region is programmed, it can be lock ed to prevent further programming, by programming the related protection bit in the otp lock bytes. ? the next higher 12 bytes of the lowest address region are reserved for future use (rfu). the bits in these rfu bytes may be programmed by the host system but it must be understood that a future device may use those bits for protection of a larger otp space. the bytes are erased when shipped from spansion. the remaining regions are erased when shipped from spansion, and are available for programming of additional permanent data. refer to figure 8.1, otp address space on page 58 for a pictorial representati on of the otp memory space. the otp memory space is intended for increased system security. otp values, such as the random number programmed by spansion, can be used to ?mate? a fl ash component with the system cpu/asic to prevent device substitution. the configuration register freeze (c r1v[0]) bit protects the entire ot p memory space from programming when set to 1. this allows trusted boot code to c ontrol programming of otp regions then set the freeze bit to prevent further otp memory space programming during the rema inder of normal power-on system operation. figure 8.1 otp address space 3 2- b yte otp region 3 1 3 2- b yte otp region 3 0 3 2- b yte otp region 29 3 2- b yte otp region 3 3 2- b yte otp region 2 3 2- b yte otp region 1 3 2- b yte otp region 0 16- b yte r a ndom n u m b er lock bit s 3 1 to 0 re s erved . . . region 0 exp a nded view when progr a mmed to 0, e a ch lock b it protect s it s rel a ted 3 2- b yte otp region from a ny f u rther progr a mming ... byte 0h byte 10h byte 1fh
november 6, 2013 s25fs-s_00_04 s25fs-s family 59 data sheet (preliminary) 8.6 registers registers are small groups of memory cells used to configure how the s25fs-s family memory device operates or to report the status of device operations. the r egisters are accessed by specific commands. the commands (and hexadecimal instruction codes) used for each register are noted in each register description. in legacy spi memory devices the individual register bi ts could be a mixture of volatile, non-volatile, or one- time programmable (otp) bits within the same register. in some conf iguration options the type of a register bit could change e.g. from non-volatile to volatile. the s25fs-s family uses separate non- volatile or volatile memory cell groups (areas) to implement the different register bit types. however, the legacy registers and commands continue to appear and behave as they always have for legacy software compatibility. there is a non-volatile and a volatile version of each legacy register when that legacy register has volatile bi ts or when the command to read the legacy register has zero read latency. when such a register is read t he volatile version of the r egister is delivered. during power-on reset (por), hardware reset, or software reset, the non-volatile version of a register is copied to the volatile version to provide the default state of th e volatile register. when non-volatile register bits are written the non-volatile version of the register is erased and programm ed with the new bit values and the volatile version of the register is updated with the new contents of the non-volatile version. when otp bits are programmed the non-volatile version of the register is programmed and the appropriate bits are updated in the volatile version of the register. when volatile regist er bits are written, only the volatile version of the register has the appr opriate bits updated. the type for each bit is noted in each register description. the default stat e shown for each bit refers to the state after power-on reset, hardware reset, or software re set if the bit is volatile. if the bit is non-volatile or otp, the default state is the value of the bit when the device is shipped fr om spansion. non-volatile bits have the same cycling (erase and program) endurance as the main flash array. table 8.13 otp address map region byte address range (hex) contents initial delivery state (hex) region 0 000 least significant byte of spansion programmed random number spansion programmed random number ... ... 00f most significant byte of spansion programmed random number 010 to 013 region locking bits byte 10 [bit 0] locks region 0 from programming when = 0 ... byte 13 [bit 7] locks region 31from programming when = 0 all bytes = ff 014 to 01f reserved for future use (rfu) all bytes = ff region 1 020 to 03f available for user programming all bytes = ff region 2 040 to 05f available for user programming all bytes = ff ... ... available for user programming all bytes = ff region 31 3e0 to 3ff available for user programming all bytes = ff
60 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 8.6.1 status register 1 8.6.1.1 status register 1 non-volatile (sr1nv) related commands: write registers (wrr 01h), r ead any register (rdar 65h), write any register (wrar 71h) status register write non-volatile (srwd_nv) sr1nv[7]: places the device in the hardware protected mode when this bit is set to 1 and the wp# input is driv en low. in this mode, the write registers (wrr) and write any register (wrar) commands (that select stat us register 1 or configuration register 1) are ignored and not accepted for execut ion, effectively locking the stat e of the status register 1 and configuration register 1 (sr1nv, sr1v, cr1nv, or cr1v ) bits, by making the registers read-only. if wp# is high, status register 1 and configuration register 1 may be changed by the wrr or wrar commands. if srwd_nv is 0, wp# has no effect and status regist er 1 and configuration register 1 may be changed by the wrr or wrar commands. wp# has no effect on th e writing of any other r egisters. the srwd_nv bit has the same non-volatile endurance as the main flash a rray. the srwd (sr1v[7]) bit serves only as a copy of the srwd_nv bit to provide zero read latency. program error default (p_err_d) sr1nv[6]: provides the default state fo r the programming error status in sr1v[6]. this bit is not user programmable. erase error (e_err) sr1v[5]: provides the default state for the erase error status in sr1v[5]. this bit is not user programmable. block protection (bp_nv2, bp _nv1, bp_nv0) sr1nv[4:2]: these bits define the main flash array area to be software-protected against program and erase commands. the bp bits are selected as either volatile or non-volatile, depending on the state of the bp non-volatile bit (bpnv_o) in the configuration register cr1nv[3]. when cr1nv[3]=0 the non-volatile version of the bp bits (sr1nv[4:2]) are used to control block protection and the wrr command writ es sr1nv[4:2] and updates sr1v[4 :2] to the same value. when cr1nv[3]=1 the volatile version of the bp bits (sr1v[4: 2]) are used to control block protection and the wrr command writes sr1v[4:2] and does not affect sr1nv[4:2] . when one or more of the bp bits is set to 1, the relevant memory area is protected against program and erase. the bulk erase (be) command can be executed only when the bp bits are cleared to 0?s. see section 9.3, block protection on page 77 for a description of how the bp bit values select the memory array area protected. the non-volatile version of the bp bits have the same non-volatile endurance as the main flash array. write enable latch defa ult (wel_d) sr1nv[1]: provides the default state fo r the wel status in sr1v[1]. this bit is programmed by spansion and is not user programmable. write-in-progress default (wip_d) sr1nv[0]: provides the default state for the wip status in sr1v[0]. this bit is programmed by spansion and is not user programmable. table 8.14 status register 1 non-volatile (sr1nv) bits field name function type default state description 7 srwd_nv status register write disable default non-volatile 0 1 = locks state of srwd, bp, and configuration register 1 bits when wp# is low by not executing wrr or wrar commands that would affect sr1nv, sr1v, cr1nv, or cr1v. 0 = no protection, even when wp# is low. 6 p_err_d programming error default non-volatile read only 0 provides the default state for the programming error status. not user programmable. 5 e_err_d erase error default non-volatile read only 0 provides the default state for the erase error status. not user programmable. 4 bp_nv2 block protection non-volatile non-volatile 000b protects the selected range of sectors (block) from program or erase when the bp bits are configured as non-volatile (cr1nv[3]=0). programmed to 111b when bp bits are configured to volatile (cr1nv[3]=1).- after which these bits are no longer user programmable. 3 bp_nv1 2 bp_nv0 1 wel_d wel default non-volatile read only 0 provides the default state for the wel status. not user programmable. 0 wip_d wip default non-volatile read only 0 provides the default state for the wip status. not user programmable.
november 6, 2013 s25fs-s_00_04 s25fs-s family 61 data sheet (preliminary) 8.6.1.2 status register 1 volatile (sr1v) related commands: read status register (rdsr1 0 5h), write registers (wrr 01h), write enable (wren 06h), write disable (wrdi 04h), clear status register (clsr 30h or 82h), read any register (rdar 65h), write any register (wrar 71h). this is th e register displayed by the rdsr1 command. status register write (srwd) sr1v[7]: srwd is a volatile copy of sr1nv[7]. this bit tracks any changes to the non-volatile version of this bit. program error (p_err) sr1v[6]: the program error bit is used as a program operation success or failure indication. when the program error bit is set to a 1 it indicates that there was an error in the last program operation. this bit will also be set when the user atte mpts to program within a protected main memory sector, or program within a locked otp region. when the program e rror bit is set to a 1 this bit can be cleared to 0 with the clear status register (clsr) command. this is a read-only bit and is not affected by the wrr or wrar commands. erase error (e_err) sr1v[5]: the erase error bit is used as an erase operation success or failure indication. when the erase error bit is set to a 1 it indica tes that there was an error in the last erase operation. this bit will also be set when the user attempts to erase an individual protected main memory sector. the bulk erase command will not set e_err if a protected sector is found during the command execution. when the erase error bit is set to a 1 this bit can be clear ed to 0 with the clear status register (clsr) command. this is a read-only bit and is not affected by the wrr or wrar commands. block protection (bp2, bp1, bp0) sr1v[4:2]: these bits define the main flash array area to be software protected against program and erase co mmands. the bp bits are selected as either volatile or non-volatile, depending on the state of the bp non- volatile bit (bpnv_o) in the configuration register cr1nv[3]. when cr1nv[3]=0 the non-volatile version of the bp bits (sr1nv [4:2]) are used to control block protection and the wrr command writes sr1nv[4:2] and updates sr1v[4:2] to the same value. when cr1nv[3]=1 the volatile version of the bp bits (sr1v[4:2]) are used to co ntrol block protection and the wrr command writes sr1v[4:2] and does not affect sr1nv[4: 2]. when one or more of the bp bits is set to 1, the relevant memory area is protected against program and erase. the bu lk erase (be) command can be executed only when the bp bits are cleared to 0?s. see section 9.3, block protection on page 77 for a description of how the bp bit values select the memory array area protected. table 8.15 status register 1 volatile (sr1v) bits field name function type default state description 7 srwd status register write disable volatile read only sr1nv volatile copy of sr1nv[7]. 6 p_err programming error occurred volatile read only 1 = error occurred. 0 = no error. 5 e_err erase error occurred volatile read only 1= error occurred. 0 = no error. 4 bp2 block protection volatile volatile protects selected range of sectors (block) from program or erase when the bp bits are configured as volatile (cr1nv[3]=1). volatile copy of sr1nv[4:2] when bp bits are configured as non-volatile. user writable when bp bits are configured as volatile. 3 bp1 2 bp0 1 wel write enable latch volatile 1 = device accepts write registers (wrr and wrar), program, or erase commands. 0 = device ignores write registers (wrr and wrar), program, or erase commands. this bit is not affected by wrr or wrar, only wren and wrdi commands affect this bit. 0 wip write-in- progress volatile read only 1= device busy, an embedded operation is in progress such as program or erase. 0 = ready device is in standby mode and can accept commands. this bit is not affected by wrr or wrar, it only provides wip status.
62 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) write enable latch (wel) sr1v[1]: the wel bit must be set to 1 to enable program, write, or erase operations as a means to provide protection against inadv ertent changes to memory or register values. the write enable (wren) command execution sets the write enable latch to a 1 to allow any program, erase, or write commands to execute afterw ards. the write disable (wrdi) co mmand can be used to set the write enable latch to a 1 to prevent all program, erase, and write commands from execution. the wel bit is cleared to 0 at the end of any successful program, writ e, or erase operation. following a failed operation the wel bit may remain set and should be cleared with a wrdi command following a clsr command. after a power-down / power-up sequence, hardware reset, or softwar e reset, the write enable latch is set to a 0 the wrr or wrar command does not affect this bit. write-in-progress (wip) sr1v[0]: indicates whether the device is performing a program, write, erase operation, or any other operation, during which a new operation command will be ignored. when the bit is set to a 1 the device is busy performing an operation. wh ile wip is 1, only read status (rdsr1 or rdsr2), read any register (rdar), erase suspend (ersp), program suspend (pgsp), clear status register (clsr), and software reset (reset) commands are ac cepted. ersp and pgsp will only be accepted if memory array erase or program operations are in prog ress. the status register e_err and p_err bits are updated while wip =1. when p_err or e_err bits are set to 1, the wip bit will remain set to 1 indicating the device remains busy and unable to receive new operat ion commands. a clear status register (clsr) command must be received to return the device to standby mode. when the wip bit is cleared to 0 no operation is in progress. this is a read-only bit. 8.6.2 status register 2 volatile (sr2v) related commands: read status register 2 (rdsr2 07h), read any register (rdar 65h). status register 2 does not have user programmable non-vola tile bits, all defined bits are volatile read only status. the default state of these bits are set by hardware. erase status (estat) sr2v[2]: the erase status bit indicates wh ether the sector, selected by an immediately preceding erase status command, complet ed the last erase command on that sector. the erase status command must be issued immediately before reading sr2v to get valid erase status. reading sr2v during a program or erase suspend does not provide valid erase status. the erase status bit can be used by system software to detect any sector that failed its last er ase operation. this can be used to detect erase operations failed due to loss of power during the erase operation. erase suspend (es) sr2v[1]: the erase suspend bit is used to determine when the device is in erase suspend mode. this is a status bit that cannot be writ ten by the user. when erase suspend bit is set to 1, the device is in erase suspend mode. when erase suspend bi t is cleared to 0, the device is not in erase suspend mode. refer to section 10.6.5, program or erase suspend (pes 85h, 75h, b0h) on page 120 for details about the erase suspend/resume commands. program suspend (ps) sr2v[0]: the program suspend bit is used to determine when the device is in program suspend mode. this is a status bit that can not be written by the user. when program suspend bit is set to 1, the device is in program suspend mode. when the program suspend bit is cleared to 0, the device is not in program suspend mode. refer to section 10.6.5, program or erase sus pend (pes 85h, 75h, b0h) on page 120 for details. table 8.16 status register 2 volatile (sr2v) bits field name function type default state description 7 rfu reserved 0 reserved for future use. 6 rfu reserved 0 reserved for future use. 5 rfu reserved 0 reserved for future use. 4 rfu reserved 0 reserved for future use. 3 rfu reserved 0 reserved for future use. 2 estat erase status volatile read only 0 1 = sector erase status command result = erase completed. 0 = sector erase status command result = erase not completed. 1 es erase suspend volatile read only 0 1 = in erase suspend mode. 0 = not in erase suspend mode. 0 ps program suspend volatile read only 0 1 = in program suspend mode. 0 = not in program suspend mode.
november 6, 2013 s25fs-s_00_04 s25fs-s family 63 data sheet (preliminary) 8.6.3 configuration register 1 configuration register 1 controls ce rtain interface and data protection f unctions. the register bits can be changed using the wrr command with sixteen input cycles or with the wrar command. 8.6.3.1 configuration register 1 non-volatile (cr1nv) related commands: write registers (wrr 01h), r ead any register (rdar 65h), write any register (wrar 71h). top or bottom protection (tbprot_o) cr1nv[5]: this bit defines the operation of the block protection bits bp2, bp1, and bp0 in the status register. as descr ibed in the status register section, the bp2-0 bits allow the user to optionally protect a por tion of the array, ranging from 1/64 , ?, ?, etc., up to the entire array. when tbprot_o is set to a 0 the block protection is def ined to start from the top (maximum address) of the array. when tbprot_o is set to a 1 the block protection is defined to start from the bottom (zero address) of the array. the tbprot_o bit is otp and set to a 0 when shipped from spansion. if tbprot_o is programmed to 1, writing the bit with a 0 does not change the value or set the program error bit (p_err in sr1v[6]). the desired state of tbprot_o must be selected during the initial configuration of the device during system manufacture; before the first program or erase operation on the main fl ash array. tbprot_o must not be programmed after programming or erasing is done in the main flash array. cr1nv[4]: reserved for future use. block protection non-volat ile (bpnv_o) cr1nv[3]: the bpnv_o bit defines whether the bp_nv 2-0 bits or the bp 2-0 bits in the status re gister are selected to control the blo ck protection feature. the bpnv_o bit is otp and cleared to a 0 with the bp_nv bits cleared to ?000? when shipped from spansion. when bpnv_o is set to a 0 the bp_nv 2-0 bits in the status regist er are selected to control the block protection and are written by the wrr command. the time required to write the bp_nv bits is t w . when bpnv is set to a 1 the bp2-0 bits in the status register are selected to co ntrol the block protection and the bp_nv 2-0 bits will be programmed to binary ?111?. this will cause the bp 2- 0 bits to be set to binary 111 after por, hardware reset, or command reset. when bpnv is set to a 1, the wrr command writes only the volatile version of the bp bits (sr1v[4:2]). the non-volatile version of the bp bits (sr1nv[4:2]) are no longer affected by the wrr command. this allows the bp bits to be written an unlim ited number of times because they are volatile and the time to write the volatile bp bits is the much faster t cs volatile register write time. if bpnv_o is programmed to 1, writing the bit with a 0 does not change the value or set the program error bit (p_err in sr1v[6]). tbparm_o cr1nv[2]: tbparm_o defines the logica l location of the paramet er block. the parameter block consists of eight 4-kb parameter sectors, which replace a 32 kb portion of the highest or lowest address sector. when tbparm_o is set to a 1 the parameter blo ck is in the top of the me mory array address space. when tbparm_o is set to a 0 the parameter block is at the bottom of the array. tbparm_o is otp and set table 8.17 configuration register 1 non-volatile (cr1nv) bits field name function type default state description 7 rfu reserved for future use non-volatile 0 reserved. 6 rfu 0 5 tbprot_o configures start of block protection otp 0 1 = bp starts at bottom (low address). 0 = bp starts at top (high address). 4 rfu reserved for future use rfu 0 reserved. 3 bpnv_o configures bp2-0 in status register otp 0 1 = volatile. 0 = non-volatile. 2 tbparm_o configures parameter sectors location otp 0 1 = 4-kb physical sectors at top, (high address). 0 = 4-kb physical sectors at bottom (low address). rfu in uniform sector configuration. 1 quad_nv quad non-volatile non-volatile 0 provides the default state for the quad bit. 0 freeze_d freeze default non-volatile read only 0 provides the default state for the freeze bit. not user programmable.
64 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) to a 0 when it ships from spansion. if tbparm_o is programmed to 1, writing the bit with a 0 does not change the value or set the program error bit (p_err in sr1v[6]). the desired state of tbparm_ o must be selected during the initial conf iguration of the de vice during system manufacture; before the first program or erase operation on the main fl ash array. tbparm_o must not be programmed after programming or erasing is done in the main flash array. tbprot_o can be set or cleared independent of the t bparm_o bit. therefore, the user can elect to store parameter information from the bottom of the array and pr otect boot code starting at the top of the array, or vice versa. or, the user can elect to store and protect the parameter information starting from the top or bottom together. when the memory array is configured as uniform sector s, the tbparm_o bit is re served for future use (rfu) and has no effect because all sectors are uniform size. quad data width non-vola tile (quad_nv) cr1nv[1]: provides the default state for the quad bit in cr1v[1]. the wrr or wrar command affects this bit. n on-volatile selection of qpi mode, by programming cr2nv[6] =1, will also program quad_nv =1 to change the non-volatile default to quad data width mode. while qpi mode is selected by cr2v[6]=1, the quad_nv bit cannot be cleared to 0. freeze protection defa ult (freeze) cr1nv[0]: provides the default state for the freeze bit in cr1v[0]. this bit is not user programmable. 8.6.3.2 configuration register 1 volatile (cr1v) related commands: read configuration register (rdcr 35h), write registers (wrr 01h), read any register (rdar 65h), write any register (wrar 7 1h). this is the register displayed by the rdcr command. tbprot, bpnv, and tbparm cr1v[5,3,2]: these bits are volatile copies of the related non-volatile bits of cr1nv. these bits track any changes to the related non-volatile version of these bits. quad data width (quad) cr1v[1]: when set to 1, this bit switches the data width of the device to 4-bit quad mode. that is, wp # becomes io2 and io3 / reset# becomes an active i/o signal when cs# is low or the reset# input when cs# is high. the wp# input is not monitored for its normal function and is internally set to high (inactive). the commands for serial, and dual i/ o read still function normally but, there is no need to drive the wp# input for those commands when switching between commands using different data path widths. similarly, there is no requirement to drive the io3 / reset # during those command s (while cs# is low). the quad bit must be set to 1 when using the quad i/o read, ddr quad i/o read, qpi mode (cr2v[6] = 1), and read quad id commands. whil e qpi mode is selected by cr2v[6]=1, the quad bit cannot be cleared to 0. the wrr command writes the n on-volatile version of the quad bit (cr1nv[1]), which also causes an update to the volat ile version cr1v[1]. the wrr command can not write the volatile version cr1v[1] without first affect ing the non-volatile version cr1nv[1] . the wrar command must be used when it is desired to write the volatile quad bit cr1v[ 1] without affecting the non -volatile version cr1nv[1]. table 8.18 configuration register 1 volatile (cr1v) bits field name function type default state description 7 rfu reserved for future use volatile cr1nv reserved. 6 rfu 5 tbprot volatile copy of tbprot_o volatile read only not user writable. see cr1nv[5] tbprot_o. 4 rfu reserved for future use rfu reserved. 3 bpnv volatile copy of bpnv_o volatile read only not user writable. see cr1nv[3] bpnv_o. 2 tbparm volatile copy of tbparm_o volatile read only not user writable. see cr1nv[2] tbparm_o. 1 quad quad i/o mode volatile 1 = quad. 0 = dual or serial. 0 freeze lock-down block protection until next power cycle volatile lock current state of block protection control bits, and otp regions. 1 = block protection and otp locked. 0 = block protection and otp unlocked.
november 6, 2013 s25fs-s_00_04 s25fs-s family 65 data sheet (preliminary) freeze protection (freeze) cr1v[0]: the freeze bit, when set to 1, lo cks the current state of the block protection control bits and otp area: ? bpnv_2-0 bits in the non-volatile status register 1 (sr1nv[4:2]) ? bp 2-0 bits in the volatile st atus register 1 (sr1v[4:2]) ? tbprot_o, tbparm_o, and bpnv_o bits in the non-vo latile configuration re gister (cr1nv[53, 2]) ? tbprot, tbparm, and bpnv bits in the volatile confi guration register (cr1v[5, 3, 2]) are indirectly protected in that they are shadows of the related cr1nv otp bits and are read only ? the entire otp memory space any attempt to change the above listed bits while freeze = 1 is prevented: ? the wrr command does not affect the list ed bits and no error status is set. ? the wrar command does not affect the list ed bits and no error status is set. ? the otpp command, with an address within the ot p area, fails and the p-err status is set. as long as the freeze bit remains cleared to logic 0 the block protection control bits and freeze are writable, and the otp addre ss space is programmable. once the freeze bit has been written to a logic 1 it can only be cleared to a logic 0 by a power-off to power- on cycle or a hardware reset. so ftware reset will not affect the state of th e freeze bit. the cr1v[0] freeze bit is volatile and the default state of freeze after power-on comes from freeze_d in cr1nv[0]. the freeze bit can be set in parallel with updating other values in cr1v by a single wrr or wrar command. the freeze bit does not prevent the wrr or wrar commands from changing the srwd_nv (sr1nv[7]), quad_nv (cr1nv[1]), or quad (cr1v[1]) bits.
66 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 8.6.4 configuration register 2 configuration register 2 controls ce rtain interface functions. the register bits can be read and changed using the read any register and write any register commands. the non-volatile version of the register provides the ability to set the por, hardware reset, or software reset state of the controls. these configuration bits are otp and may only have their default state changed to the opposite value one time during system configuration. the volatile versio n of the register controls the f eature behavior during normal operation. 8.6.4.1 configuration register 2 non-volatile (cr2nv) related commands: read any register (rda r 65h), write any register (wrar 71h). address length non-volatile cr2nv[7]: this bit controls the por, hardware reset, or software reset state of the expected address length for all commands that require address and are not fixed 3-byte only or 4-byte (32-bit) only address. most commands that need an ad dress are legacy spi commands that traditionally used 3-byte (24-bit) address. for device densities greater than 128 mbit a 4-byte address is required to access the entire memory array. the address length configuratio n bit is used to change most 3-byte address commands to expect 4-byte address. see table 10.1, s25fs-s family command set (sorted by function) on page 88 for command address length. the use of 4-byte address le ngth also applies to the 128-mbit member of the s25fs-s family so that the same 4-byte address hardwa re and software interface may be used for all family members to simplify migration between densities. t he 128-mbit member of the s25fs-s family simply ignores the content of the fourth, high order, address byte . this non-volatile address length configuration bit enables the device to start immediat ely (boot) in 4-byte address mode rather than the legacy 3-byte address mode. qpi non-volatile cr2nv[6]: this bit controls the por, hardware re set, or software reset state of the expected instruction width for all commands. legacy spi commands always send the instruction one bit wide (serial i/o) on the si (io0) signal. the s25fs-s family also supports the qpi mode in which all transfers between the host system and memory ar e 4-bits wide on io0 to io3, incl uding all instruct ions. this non- volatile qpi configuration bit enables the device to start immediately (boot) in qpi mode rather than the legacy serial instruction mode. when this bit is programmed to qpi mode, the quad_nv bit is also programmed to quad mode (cr1nv[1]=1). the recommended procedure for moving to qpi mode is to first use the wrar command to set cr2v[6]=1, qpi mode. t he volatile register write for qpi mode has a short and well defined time (t cs ) to switch the device interface into qpi mode. following commands can then be immediately sent in qpi protocol. the wrar command can be used to program cr2nv[6]=1, followed by polling of sr1v[0] to know when the programming operati on is completed. similarly, to exit qpi mode, the wrar command is used to clear cr2v[6]=0. cr2 nv[6] cannot be erased to 0 because it is otp. io3 reset non-volatile cr2nv[5]: this bit controls the por, hardware reset, or software reset state of the io3 signal behavior. most legacy spi devices do not ha ve a hardware reset input signal due to the limited signal count and connections available in traditional spi device packages. the s25fs-s family provides the option to use the io3 signal as a hardware reset input when the io3 signal is not in use for transferring information between the host system and the memory. this non-volatile io3 reset configuration bit enables the device to start immediately (boot) with io3 enabled for use as a reset# signal. table 8.19 configuration register 2 non-volatile (cr2nv) bits field name function type default state description 7 al_nv address length otp 0 1 = 4-byte address. 0 = 3-byte address. 6 qa_nv qpi 0 1 = enabled - qpi (4-4-4) protocol in use. 0 = disabled - legacy spi protocols in use, instruction is always serial on si. 5 io3r_nv io3 reset 0 1 = enabled - io3 is used as reset# input when cs# is high or quad mode is disabled cr1v[1]=1. 0 = disabled - io3 has no alternate function, hardware reset is disabled. 4 rfu reserved 0 reserved for future use. 3 rl_nv read latency 1 0 to 15 latency (dummy) cycles following read address or continuous mode bits. note that bit 3 has a default value of 1 and may be programmed one time to 0 but cannot be returned to 1. 2 0 1 0 0 0
november 6, 2013 s25fs-s_00_04 s25fs-s family 67 data sheet (preliminary) read latency non-volatile cr2nv[3:0]: this bit controls the por, hardwa re reset, or software reset state of the read latency (dummy cycle) delay in all variable latency read commands. the following read commands have a variable latency period between the e nd of address or mode and the beginning of read data returning to the host: ? fast read ? dual i/o read ? quad i/o read ? ddr quad i/o read ? otpr ? rdar this non-volatile read lat ency configuration bit sets the number of read laten cy (dummy cycles) in use so the device can start immediately (boot) with an appropriate read latenc y for the host system. notes: 1. sck frequency > 133 mhz sdr, or 80 mhz ddr is not supported by this family of devices. 2. the dual i/o, quad i/o, qpi, ddr quad i/o, and ddr qpi, comma nd protocols include continuous read mode bits following the address. the clock cycles for these bits ar e not counted as part of the latency cycles shown in the table. example: the legacy quad i/o command has 2 continuous read mode cycles following the address. ther efore, the legacy quad i/o command without additional read latency is supported only up to the frequency shown in the table for a read latency of 0 cycles. by increasing the variable read latency the frequency of the quad i/o command can be increased to allow operation up to the maximum supported 133 mhz frequency. 3. other read commands have fixed latency, e.g. read always has zero read latency. rsfdp alwa ys has eight cycles of latency. 4. ddr qpi is only supported for latency cycles 1 through 5 and for clock frequency of up to 68 mhz. table 8.20 latency code (cycles) versus frequency latency cycles read command maximum frequency (mhz) fast read (1-1-1) otpr (1-1-1) rdar (1-1-1) rdar (4-4-4) dual i/o (1-2-2) quad i/o (1-4-4) qpi (4-4-4) ddr quad i/o (1-4-4) ddr qpi (4-4-4) (note 4) mode cycles = 0 mode cycles = 4 mode cycles = 2 mode cycles = 1 0508040n/a 166925322 2 80 104 66 34 3 92 116 80 45 4 104 129 92 57 5 116 133 104 68 6 129 133 116 80 7 133 133 129 80 8 133 133 133 80 9 133 133 133 80 10 133 133 133 80 11 133 133 133 80 12 133 133 133 80 13 133 133 133 80 14 133 133 133 80 15 133 133 133 80
68 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 8.6.4.2 configuration register 2 volatile (cr2v) related commands: read any register (rdar 65h), write any register (wrar 71h), 4bam. address length cr2v[7]: this bit controls the expected address length for all commands that require address and are not fixed 3-byte only or 4-byte (32-bit) only address. see table 10.1, s25fs-s family command set (sorted by function) on page 88 for command address length. this volatile address length configuration bit enables the address length to be changed during normal operation. the 4-byte address mode (4bam) command directly sets th is bit into 4-byte address mode. qpi cr2v[6]: this bit controls the expected instructi on width for all commands. this volatile qpi configuration bit enables the device to enter and exit qpi mode during normal operation. when this bit is set to qpi mode, the quad bit is also set to quad mode (c r1v[1]=1). when this bit is cleared to legacy spi mode, the quad bit is not affected. io3 reset cr2v[5]: this bit controls the io3 / reset# signal b ehavior. this volatile io3 reset co nfiguration bit enables the use of io3 as a r eset# input during no rmal operation. read latency cr2v[3:0]: this bit controls the read latency (du mmy cycle) delay in va riable latency read commands these volatile configuration bits enable t he user to adjust the read latency during normal operation to optimize the latency for different command s or, at different operating frequencies, as needed. table 8.21 configuration register 2 volatile (cr2v) bits field name function type default state description 7 al address length volatile cr2nv 1 = 4 byte address. 0 = 3 byte address. 6 qa qpi 1 = enabled - qpi (4-4-4) protocol in use. 0 = disabled - legacy spi protocols in use, instruction is always serial on si. 5 io3r_s io3 reset 1 = enabled - io3 is used as reset# input when cs# is high or quad mode is disabled cr1v[1]=1. 0 = disabled - io3 has no alternate function, hardware reset is disabled. 4 rfu reserved reserved for future use. 3 rl read latency 0 to 15 latency (dummy) cycles following read address or continuous mode bits. 2 1 0
november 6, 2013 s25fs-s_00_04 s25fs-s family 69 data sheet (preliminary) 8.6.5 configuration register 3 configuration register 3 controls certain command be haviors. the register bits can be read and changed using the read any register and write any register co mmands. the non-volatile register provides the por, hardware reset, or software reset state of the co ntrols. these configuration bits are otp and may be programmed to their opposite state one time during syst em configuration if needed. the volatile version of configuration register 3 allows the configuration to be changed dur ing system operat ion or testing. 8.6.5.1 configuration register 3 non-volatile (cr3nv) related commands: read any register (rda r 65h), write any register (wrar 71h). blank check non-volatile cr3nv[5]: this bit controls the por, hardware reset, or software reset state of the blank check during erase feature. 02h non-volatile cr3nv[4]: this bit controls the por, hardware rese t, or software reset state of the page programming buffer address wrap point. 20h non-volatile cr3nv[3]: this bit controls the por, hardware re set, or software reset state of the availability of 4-kb parameter sectors in the main flash array address map. 30h non-volatile cr3nv[2]: this bit controls the por, hardware rese t, or software reset state of the 30h instruction code is used. d8h non-volatile cr3nv[1]: this bit controls the por, hardware re set, or software reset state of the configuration for the size of the area erased by the d8h or dch instructions. f0h non-volatile cr3nv[0]: this bit controls the por, hardware reset, or software reset state of the availability of the spansion legacy fl-s family software re set instruction. table 8.22 configuration register 3 non-volatile (cr3nv) bits field name function type default state description 7 rfu reserved otp 0 reserved for future use. 6 rfu reserved 0 reserved for future use. 5 bc_nv blank check 0 1 = blank check during erase enabled. 0 = blank check disabled. 4 02h_nv page buffer wrap 0 1 = wrap at 512 bytes. 0 = wrap at 256 bytes. 3 20h_nv 4-kb erase 0 1 = 4-kb erase disabled (uniform sector architecture). 0 = 4-kb erase enabled (hybrid sector architecture). 2 30h_nv clear status / resume select 0 1 = 30h is erase or program resume command. 0 = 30h is clear status command. 1 d8h_nv block erase size 0 1 = 256-kb erase. 0 = 64-kb erase. 0 f0h_nv legacy software reset enable 0 1 = f0h software reset is enabled. 0 = f0h software reset is disabled (ignored).
70 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 8.6.5.2 configuration register 3 volatile (cr3v) related commands: read any register (rda r 65h), write any register (wrar 71h). blank check volatile cr3v[5]: this bit controls the blank check duri ng erase feature. when this feature is enabled an erase command first evaluates the erase status of the sector. if the sector is found to have not completed its last erase successfully, the sector is unconditionally erased. if the last erase was successful, the sector is read to determine if the sector is still erased (blank). the erase oper ation is started immediately after finding any programmed zero. if the sector is already blank (no programmed zero bit found) the remainder of the erase operation is skipped. this ca n dramatically reduce erase time when sectors being erased do not need the erase operat ion. when enabled the blank check feature is used within the parameter erase, sector erase, and bulk erase commands. when blank check is disabled an erase command unconditionally starts the erase operation. 02h volatile cr3v[4]: this bit controls the page programming buffer address wrap point. legacy spi devices generally have used a 256-byte page programmi ng buffer and defined that if data is loaded into the buffer beyond the 255-byte location, the address at which additional bytes are loaded would be wrapped to address zero of the buffer. the s25fs-s family pr ovides a 512-byte page programming buffer that can increase programming performance. for legacy software compatibility, this configuration bit provides the option to continue the wrapping behavior at the 256-byt e boundary or to enable full use of the available 512-byte buffer by not wrapping the load address at the 256-byte boundary. 20h volatile cr3v[3]: this bit controls the availability of 4-kb parameter sectors in the main flash array address map. the parameter sectors can overlay the hig hest or lowest 32-kb address range of the device or they can be removed from the address map so that all sect ors are uniform size. this bit shall not be written to a value different than the value of cr3nv[3]. the value of cr3v[3] may only be changed by writing cr3nv[3]. 30h volatile cr3v[2]: this bit controls how the 30h instruction c ode is used. the instruction may be used as a clear status command or as an alternate progra m / erase resume command. this allows software compatibility with either spansion legacy spi devices or alternate vendor devices. d8h volatile cr3v[1]: this bit controls the area erased by the d8h or dch instructions. the instruction can be used to erase 64-kb physical sectors or 256-kb si ze and aligned blocks. the option to erase 256-kb blocks in the lower density family members allows for consistent software behavio r across all densities that can ease migration between different densities. f0h volatile cr3v[0]: this bit controls the availability of the spansion legacy fl-s family software reset instruction. the s25fs-s family s upports the industry common 66h + 99h instruction sequence for software reset. this configuration bit allows the option to cont inue use of the legacy f0h single command for software reset. table 8.23 configuration register 3 volatile (cr3v) bits field name function type default state description 7 rfu reserved volatile cr3nv reserved for future use. 6 rfu reserved reserved for future use. 5 bc_v blank check 1 = blank check during erase enabled. 0 = blank check disabled. 4 02h_v page buffer wrap 1 = wrap at 512 bytes. 0 = wrap at 256 bytes. 3 20h_v 4-kb erase volatile, read only 1 = 4-kb erase disabled (uniform sector architecture). 0 = 4-kb erase enabled (hybrid sector architecture). 2 30h_v clear status / resume select volatile 1 = 30h is erase or program resume command. 0 = 30h is clear status command. 1 d8h_v block erase size 1 = 256-kb erase. 0 = 64-kb erase. 0 f0h_v legacy software reset enable 1 = f0h software reset is enabled. 0 = f0h software reset is disabled (ignored).
november 6, 2013 s25fs-s_00_04 s25fs-s family 71 data sheet (preliminary) 8.6.6 configuration register 4 configuration register 4 controls the main flash ar ray read commands burst wrap behavior. the burst wrap configuration does not affect comm ands reading from areas other than the main flash array e.g. read commands for registers or otp array. the non-volatile ve rsion of the register provides the ability to set the start up (boot) state of the controls as the contents are copied to the volat ile version of the register during the por, hardware reset, or software reset. the volatile version of the register co ntrols the feature behavior during normal operation. the register bits can be read and changed using the read any register and write any register commands. the volatile version of the register can also be written by the set burst length (c0h) command. 8.6.6.1 configuration register 4 non-volatile (cr4nv) related commands: read any register (rda r 65h), write any register (wrar 71h). output impedance non- volatile cr4nv[7:5]: these bits control the por, hardware reset, or software reset state of the io signal output impedance (drive st rength). multiple drive strength are available to help match the output impedance with the system printed ci rcuit board environment to minimize overshoot and ringing. these non-volatile output im pedance configuration bits enable the device to start immediately (boot) with the appropriate drive strength. wrap enable non-volatile cr4nv[4]: this bit controls the por, hardwar e reset, or software reset state of the wrap enable. the commands affected by wrap enable are: quad i/o read, and ddr quad i/o read. this configuration bit enables the device to start imm ediately (boot) in wrapped burst read mode rather than the legacy sequential read mode. wrap length non-volatile cr4nv[1:0]: these bits controls the por, ha rdware reset, or software reset state of the wrapped read length and alignment. these non-volatile confi guration bits enable the device to start immediately (boot) in wrapped burst read m ode rather than the legacy sequential read mode. table 8.24 configuration register 4 non-volatile (cr4nv) bits field name function type default state description 7 oi_o output impedance otp 0 see table 8.25, output impedance control on page 71 . 6 0 5 0 4 we_o wrap enable 1 0 = wrap enabled. 1 = wrap disabled. 3 rfu reserved 0 reserved for future use. 2 rfu reserved 0 reserved for future use. 1 wl_o wrap length 0 00 = 8-byte wrap. 01 = 16-byte wrap. 10 = 32-byte wrap. 11 = 64-byte wrap. 0 0 table 8.25 output impedance control cr4nv[7:5] impedance selection typical impedance to v ss (ohms) typical impedance to v dd (ohms) notes 000 47 45 factory default 001 124 105 010 71 64 011 47 45 100 34 35 101 26 28 110 22 24 111 18 21
72 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 8.6.6.2 configuration register 4 volatile (cr4v) related commands: read any register (rdar 65h), write any register (wrar 71h), set burst length (sbl c0h). output impedance cr2v[7:5]: these bits control the io signal output impedance (drive strength). this volatile output impedance configurat ion bit enables the user to adjus t the drive strengt h during normal operation. wrap enable cr4v[4]: this bit controls the burst wrap feature. this volatile configuration bit enables the device to enter and exit burst wrapped read mode during normal operation. wrap length cr4v[1:0]: these bits controls the wrapped read length and alignment during normal operation. these volatile configuration bits enable the user to adjust the burst wrapped read length during normal operation. table 8.26 configuration register 4 volatile (cr4v) bits field name function type default state description 7 oi output impedance volatile cr4nv see table 8.25, output impedance control on page 71 . 6 5 4 we wrap enable 0 = wrap enabled. 1 = wrap disabled. 3 rfu reserved reserved for future use. 2 rfu reserved reserved for future use. 1 wl wrap length 00 = 8-byte wrap. 01 = 16-byte wrap. 10 = 32-byte wrap. 11 = 64-byte wrap. 0
november 6, 2013 s25fs-s_00_04 s25fs-s family 73 data sheet (preliminary) 8.6.7 asp regi ster (aspr) related commands: asp read (asp rd 2bh) and asp program (aspp 2f h), read any register (rdar 65h), write any register (wrar 71h). the asp register is a 16-bit otp memory location used to permanently configure the behavior of advanced sector protection (asp) features. aspr does not have us er programmable volatile bits, all defined bits are otp. the default state of the aspr bits are programmed by spansion. password protection mode lo ck bit (pwdmlb) aspr[2]: when programmed to 0, the password protection mode is pe rmanently selected. persistent protection mode lock bit (pstmlb) aspr[1]: when programmed to 0, the persistent protection mode is pe rmanently selected. pwdmlb (aspr[2]) and pstmlb (aspr[1 ]) are mutually exclusive, onl y one may be programmed to 0. aspr bits may only be programmed while aspr[2:1] = 11b. attempti ng to program aspr bits when aspr[2:1] is not = 11b will result in a programming error wit h p_err (sr1v[6]) set to 1. after the asp protection mode is selected by programming aspr[2:1] = 10b or 01b, the state of all aspr bits are locked and permanently protected from further programming. attempting to program aspr[2:1] = 00b will result in a programming error with p_err (sr1v[6]) set to 1. similarly, otp configuration bits li sted in the asp register description ( asp register on page 81 ), may only be programmed while aspr[2:1] = 11b. the otp configur ation must be selected before selecting the asp protection mode. the otp configur ation bits are permanently protec ted from further change when the asp protection mode is selected. atte mpting to program these otp configur ation bits when aspr[2:1] is not = 11b will result in a programming e rror with p_err (sr1v[6]) set to 1. the asp protection mode should be selected during system configuration to ensure that a malicious program does not select an undesired protection mode at a later ti me. by locking all the prot ection configuration via the asp mode selection, later alterati on of the protection methods by malicious programs is prevented. table 8.27 asp register (aspr) bits field name function type default state description 15 to 9 rfu reserved otp 1 reserved for future use. 8 rfu reserved otp 1 reserved for future use. 7 rfu reserved otp 1 reserved for future use. 6 rfu reserved otp 1 reserved for future use. 5 rfu reserved otp 1 reserved for future use. 4 rfu reserved rfu 1 reserved for future use. 3 rfu reserved rfu 1 reserved for future use. 2 pwdmlb password protection mode lock bit otp 1 0 = password protection mode permanently enabled. 1 = password protection mode not permanently enabled. 1 pstmlb persistent protection mode lock bit otp 1 0 = persistent protection mode permanently enabled. 1 = persistent protection mode not permanently enabled. 0 rfu reserved rfu 1 reserved for future use.
74 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 8.6.8 password register (pass) related commands: password read (passrd e7h) and password program (passp e8h), read any register (rdar 65h), write any regi ster (wrar 71h). the pass register is a 64-bit otp memory location used to permanently define a password for the adva nced sector protection (asp) feature. pass does not have user programmable volatile bits, all defined bits ar e otp. a volatile copy of pass is used to satisfy read latency requirements but the volatile register is not user writable or further described. 8.6.9 ppb lock register (ppbl) related commands: ppb lock read (plbrd a7h, plbwr a6h), read any register (rdar 65h). ppbl does not have separate user programmable non-volatil e bits, all defined bits are volatile read only status. the default state of the rfu bits is set by hard ware. the default state of the ppblock bit is defined by the asp protection mode bits in aspr[2:1]. ther e is no non-volatile version of the ppbl register. the ppblock bit is used to protect the ppb bits. when ppbl[0] = 0, the ppb bits can not be programmed. 8.6.10 ppb access register (ppbar) related commands: ppb read (ppbrd fch or 4ppb rd e2h), ppb program (ppbp fdh or 4ppbp e3h), ppb erase (ppbe e4h). ppbar does not have user writable volatile bits, all ppb a rray bits are non-volatile. the default state of the ppb array is erased to ffh by spansion. there is no volatile versi on of the ppbar register. table 8.28 password register (pass) bits field name function type default state description 63 to 0 pwd hidden password otp ffffffff- ffffffffh non-volatile otp storage of 64-bit password. the password is no longer readable after the password protection mode is selected by programming asp register bit 2 to 0. table 8.29 ppb lock register (ppbl) bits field name function type default state description 7 to 1 rfu reserved volatile 00h reserved for future use 0 ppblock protect ppb array volatile read only aspr[2:1] = 1xb = persistent protection mode = 1 aspr[2:1] = 01b = password protection mode = 0 0 = ppb array protected. 1 = ppb array may be programmed or erased. table 8.30 ppb access register (ppbar) bits field name function type default state description 7 to 0 ppb read or program per sector ppb non-volatile ffh 00h = ppb for the sector addressed by the ppbrd or ppbp command is programmed to 0, protecting that sector from program or erase operations. ffh = ppb for the sector addressed by the ppbrd command is 1, not protecting that sector from program or erase operations.
november 6, 2013 s25fs-s_00_04 s25fs-s family 75 data sheet (preliminary) 8.6.11 dyb access register (dybar) related commands: dyb read (dybrd fah or 4dybrd e0h) and dyb write (dybwr fbh or 4dybwr e1h). dybar does not have user programmable non-volatile bi ts, all bits are a representatio n of the volatile bits in the dyb array. the default state of the dyb array bits is set by hardware. there is no non-volatile version of the dybar register. 8.6.12 spi ddr data learning registers related commands: program nvdlr (pnvdlr 43h), write vdlr (wvdlr 4ah), data learning pattern read (dlprd 41h), read any register (r dar 65h), write any register (wrar 71h). the data learning pattern (dlp) resides in an 8-bit non-volatile data learning register (nvdlr) as well as an 8-bit volatile data learning register (vdlr). when shipped from spansion, the nvdlr value is 00h. once programmed, the nvdlr cannot be reprogrammed or erased; a copy of the data pattern in the nvdlr will also be written to the vdlr. the vdlr can be writt en to at any time, but on reset or power cycles the data pattern will revert back to what is in the nvdl r. during the learning phase described in the spi ddr modes, the dlp will come from the vdlr. each io will ou tput the same dlp value for every clock edge. for example, if the dlp is 34h (or binary 00110100) t hen during the first clock edge all io?s will output 0; subsequently, the 2nd clock edge all i/o?s will output 0, the 3r d will output 1, etc. when the vdlr value is 00h, no preamble data pattern is presented during the dummy phase in the ddr commands. table 8.31 dyb access register (dybar) bits field name function type default state description 7 to 0 dyb read or write per sector dyb volatile ffh 00h = dyb for the sector addressed by the dybrd or dybwr command is cleared to 0, protecting that sector from program or erase operations. ffh = dyb for the sector addressed by the dybrd or dybwr command is set to 1, not protecting that sector from program or erase operations. table 8.32 non-volatile data learning register (nvdlr) bits field name function type default state description 7 to 0 nvdlp non-volatile data learning pattern otp 00h otp value that may be transferred to the host during ddr read command latency (dummy) cycles to provide a training pattern to help the host more accurately center the data capture point in the received data bits. table 8.33 volatile data learning register (vdlr) bits field name function type default state description 7 to 0 vdlp volatile data learning pattern volatile takes the value of nvdlr during por or reset volatile copy of the nvdlp used to enable and deliver the data learning pattern (dlp) to the outputs. the vdlp may be changed by the host during system operation.
76 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 9. data protection 9.1 secure silicon region (otp) the device has a 1024 byte one-time program (otp) addr ess space that is separate from the main flash array. the otp area is divided into 32, individual ly lockable, 32-byte aligned and length regions. the otp memory space is intended for increased system security. otp values can ?mate? a flash component with the system cpu/asic to prevent device substitution. see otp address space on page 58 , otp program (otpp 42h) on page 123 , and otp read (otpr 4bh) on page 123 . 9.1.1 reading otp memory space the otp read command uses the same protocol as fa st read. otp read operations outside the valid 1-kb otp address range will yield indeterminate data. 9.1.2 programming otp memory space the protocol of the otp programmi ng command is the same as page program. the otp program command can be issued multiple times to any given otp address, but this address space can never be erased. the valid address range for otp program is depicted in figure 8.1, otp address space on page 58 . otp program operations outside the valid otp address range will be ignored, without p_err in sr1v set to 1. otp program operations within the valid otp addr ess range, while freeze = 1, will fail with p_err in sr1v set to 1. the otp address space is not protecte d by the selection of an asp protection mode. the freeze bit (cr1v[0]) may be used to protect the otp address space. 9.1.3 spansion prog rammed random number spansion standard practice is to progr am the low order 16 bytes of the ot p memory space (locations 0x0 to 0xf) with a 128-bit random number using the linear co ngruential random number method. the seed value for the algorithm is a random number concatenate d with the day and time of tester insertion. 9.1.4 lock bytes the lsb of each lock byte protects the lowest addres s region related to the byte, the msb protects the highest address region related to the byte. the next hig her address byte similarly protects the next higher 8 regions. the lsb bit of the lowest address lock byte protects the higher address 16 bytes of the lowest address region. in other words, the lsb of location 0x 10 protects all the lock bytes and rfu bytes in the lowest address region from further programming. see otp address space on page 58 .
november 6, 2013 s25fs-s_00_04 s25fs-s family 77 data sheet (preliminary) 9.2 write enable command the write enable (wren) command must be written prio r to any command that modifies non-volatile data. the wren command sets the write enable latch (wel) bit. the wel bit is cleared to 0 (disables writes) during power-up, hardware reset, or after the device completes the following commands: reset page program (pp or 4pp) parameter 4-kb erase (p4e or 4p4e) sector erase (se or 4se) bulk erase (be) write disable (wrdi) write registers (wrr) write any register (wrar) otp byte programming (otpp) advanced sector protecti on register program (aspp) persistent protection bit program (ppbp) persistent protection bit erase (ppbe) password program (passp) program non-volatile data learning register (pnvdlr) 9.3 block protection the block protect bits (status register bits bp2, bp1 , bp0) in combination with the configuration register tbprot_o bit can be used to protect an address range of the main flash array from program and erase operations. the size of the range is determined by the value of the bp bits and the upper or lower starting point of the range is selected by the tbprot_o bit of the configuration register (cr1nv[5]). table 9.1 upper array start of protection (tbprot_o = 0) status register content protected fraction of memory array protected memory (kbytes) bp2 bp1 bp0 fs128s 128 mb fs256s 256 mb 0 0 0none0 0 0 0 1 upper 64th 256 512 0 1 0 upper 32nd 512 1024 0 1 1 upper 16th 1024 2048 1 0 0 upper 8th 2048 4096 1 0 1 upper 4th 4096 8192 1 1 0 upper half 8192 16384 1 1 1 all sectors 16384 32768
78 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) when block protection is enabled (i.e ., any bp2-0 are set to 1), advanced sector protection (asp) can still be used to protect sectors not protected by the block pr otection scheme. in the case that both asp and block protection are used on the same sector the logical or of asp and block protection related to the sector is used. 9.3.1 freeze bit bit 0 of configuration register 1 (cr1v[0]) is the freeze bit. the freeze bit, when set to 1, locks the current state of the block protection control bits and otp area un til the next power off-on cycle. additional details in configuration register 1 volatile (cr1v) on page 64 . 9.3.2 write protect signal the write protect (wp#) input in combination with the st atus register write disable (srwd) bit (sr1nv[7]) provide hardware input signal c ontrolled protection. when wp# is low and srwd is set to 1 status register 1 (sr1nv and sr1v) and configuration register 1 (cr1nv and cr1v) are protected from alteration. this prevents disabling or changing the protection defined by the block protect bits. see status register 1 on page 60 . 9.4 advanced sector protection advanced sector protection (asp) is the name used for a set of independent hardware and software methods used to disable or enable programming or eras e operations, individually, in any or all sectors. every main flash array sector has a non-volatile pers istent protection bit (ppb) and a volatile dynamic protection bit (dyb) associated with it. when either bit is 0, the sector is protected from program and erase operations. the ppb bits are protected from program and erase when the volatile ppb lock bit is 0. there are two methods for managing the state of the ppb lock bi t: password protection an d persistent protection. an overview of these methods is shown in figure 9.2, advanced sector protection overview on page 80 . block protection and asp protection settings for each sect or are logically ored to define the prot ection for each sector i.e. if either mechanism is protecting a sector the se ctor cannot be programmed or erased. refer to block protection on page 77 for full details of the bp2-0 bits. table 9.2 lower array start of protection (tbprot_o = 1) status register content protected fraction of memory array protected memory (kbytes) bp2 bp1 bp0 fs128s 128 mb fs256s 256 mb 0 0 0none0 0 0 0 1 lower 64th 256 512 0 1 0 lower 32nd 512 1024 0 1 1 lower 16th 1024 2048 1 0 0 lower 8th 2048 4096 1 0 1 lower 4th 4096 8192 1 1 0 lower half 8192 16384 1 1 1 all sectors 16384 32768
november 6, 2013 s25fs-s_00_04 s25fs-s family 79 data sheet (preliminary) figure 9.1 sector protection control s ector 0 logic a l or s ector 0 s ector 0 block s ector 1 logic a l or s ector 1 s ector 1 s ector n logic a l or s ector n s ector n ... ... ... ... protection logic per s i s tent protection bit s arr a y (ppb) dyn a mic protection bit s arr a y (dyb) fl as h memory arr a y
80 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) figure 9.2 advanced sector protection overview the persistent protecti on method sets the ppb lock bit to 1 during por, or ha rdware reset so that the ppb bits are unprotected by a device reset. there is a co mmand to clear the ppb lock bi t to 0 to protect the ppb. there is no command in the persist ent protection method to set the ppb lock bit to 1, therefore the ppb lock bit will remain at 0 until the next power-off or ha rdware reset. the persistent protection method allows boot code the option of chang ing sector protection by programming or erasing th e ppb, then pr otecting the ppb from further change for the remainder of normal syst em operation by clearing the ppb lock bit to 0. this is sometimes called boot-code controlled sector protection. power on / re s et a s pr[2]=0 a s pr[1]=0 ppblock = 0 ppb bit s locked ppblock = 1 ppb bit s er asab le a s pr bit s locked a s pr bit s locked a s pr bit s are progr a mm ab le a nd progr a mm ab le p ass word unlock ppblock = 1 ppb bit s er asab le a nd progr a mm ab le p ass word protection per s i s tent protection def au lt per s i s tent protection ppb lock bit write ppb lock bit write ppblock = 0 ppb bit s locked ye s ye s ye s ye s ye s no no no no no p ass word protection mode protect s the per s i s tent protection mode doe s not def au lt mode a llow s protect the ppb a fter power u p. the b it s m a y b e ch a nged. a ppb lock bit write comm a nd protect s the ppb b it s u ntil the next power-off or re s et. ppb a fter power u p. a p ass word u nlock comm a nd will en ab le ch a nge s to ppb. a ppb lock bit write comm a nd t u rn s protection ba ck on. a s pr to b e progr a mmed to perm a nently s elect the protection mode. the def au lt mode otherwi s e a ct s the sa me as the per s i s tent protection mode. after one of the protection mode s i s s elected, a s pr i s no longer progr a mm ab le, m a king the s elected protection mode perm a nent.
november 6, 2013 s25fs-s_00_04 s25fs-s family 81 data sheet (preliminary) the password method clears the ppb lock bit to 0 during por, or hardware reset to protect the ppb. a 64- bit password may be permanently programmed and hi dden for the password method. a command can be used to provide a password for comparison with the hidden password. if the password matches, the ppb lock bit is set to 1 to unprotect the ppb. a command c an be used to clear the ppb lock bit to 0. this method requires use of a password to control ppb protection. the selection of the ppb lock bit management met hod is made by programming otp bits in the asp register so as to permanently select the method used. 9.4.1 asp register the asp register is used to permanently configur e the behavior of advanced sector protection (asp) features. see table 8.27, asp register (aspr) on page 73 . as shipped from the factory, all dev ices default asp to the persistent protection mode, with all sectors unprotected, when power is applied. the device program mer or host system must then choose which sector protection method to use. progra mming either of the, one-time programmable, protection mode lock bits, locks the part permanently in the selected mode: ? aspr[2:1] = ?11? = no asp mode selected, pe rsistent protection mode is the default. ? aspr[2:1] = ?10? = persistent prot ection mode permanently selected. ? aspr[2:1] = ?01? = password protec tion mode permanently selected. ? aspr[2:1] = ?00? is an illega l condition, attemp ting to program more than one bit to zero results in a programming failure. asp register prog ramming rules: ? if the password mode is chosen, the password must be programmed prior to setting the protection mode lock bits. ? once the protection mode is selected, the followi ng otp configuration register bits are permanently protected from programming and no further change s to the otp register bits is allowed: ? cr1nv[5:2] ? cr2nv ? cr3nv ? cr4nv ? aspr ? pass ?nvdlr ? if an attempt to change any of the registers above, after the asp mode is selected, the operation will fail and p_err (sr1v[6]) will be set to 1. the programming time of the asp r egister is the same as the typica l page programming time. the system can determine the status of the asp register programming operation by reading the wip bit in the status register. see status register 1 on page 60 for information on wip. see sector protection states summary on page 83 .
82 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 9.4.2 persistent protection bits the persistent protection bits (ppb) are located in a separate non-volatile flash array. one of the ppb bits is related to each sector. when a ppb is 0, its related se ctor is protected from pr ogram and erase operations. the ppb are programmed individually but must be erased as a group, similar to the way individual words may be programmed in the main array but an entire sector must be erased at the same time. the ppb have the same program and erase endurance as the main flash me mory array. preprogramming and verification prior to erasure are handled by the device. programming a ppb bit requires the typical page progra mming time. erasing all the ppbs requires typical sector erase time. during ppb bit progra mming and ppb bit erasing, status is available by reading the status register. reading of a ppb bit requires the initial access time of the device. notes: 1. each ppb is individually programmed to 0 and all are erased to 1 in parallel. 2. if the ppb lock bit is 0, the ppb program or ppb erase co mmand does not ex ecute and fails without programming or erasing the ppb. 3. the state of the ppb for a given sector can be verified by using the ppb read command. 9.4.3 dynamic protection bits dynamic protection bits are volatile and unique for each sector and can be individually modified. dyb only control the protection for sectors t hat have their ppb set to 1. by issu ing the dyb write command, a dyb is cleared to 0 or set to 1, thus placing each sector in the protected or unprotecte d state respectively. this feature allows software to easily protect sectors agai nst inadvertent changes, yet does not prevent the easy removal of protection when changes are needed. the dybs can be set or cleared as often as needed as they are volatile bits. 9.4.4 ppb lock bit (ppbl[0]) the ppb lock bit is a volatile bit for protecting all ppb bits. wh en cleared to 0, it locks all ppbs, when set to 1, it allows the ppbs to be changed. see section 8.6.9, ppb lock register (ppbl) on page 74 for more information. the plbwr command is used to cl ear the ppb lock bit to 0. the ppb lo ck bit must be cl eared to 0 only after all the ppbs are configured to the desired settings. in persistent protection m ode, the ppb lock is set to 1 during por or a hardware reset. when cleared to 0, no software command sequence can set the ppb lock bit to 1, only another hardware reset or power-up can set the ppb lock bit. in the password protection m ode, the ppb lock bit is clea red to 0 during por or a hardware reset. the ppb lock bit can only be set to 1 by the password unlock command.
november 6, 2013 s25fs-s_00_04 s25fs-s family 83 data sheet (preliminary) 9.4.5 sector protection states summary each sector can be in one of the following protection states: ? unlocked ? the sector is unprot ected and protection can be changed by a simple command. the protection state defaults to unprotected when the device is shipped from spansion. ? dynamically locked ? a sector is protected and pr otection can be changed by a simple command. the protection state is not saved across a power cycle or reset. ? persistently locked ? a sector is protected and pr otection can only be changed if the ppb lock bit is set to 1. the protection state is non-volat ile and saved across a power cycle or reset. changi ng the protection state requires programming and or erase of the ppb bits. 9.4.6 persistent protection mode the persistent protecti on method sets the ppb lock bit to 1 during por or ha rdware reset so that the ppb bits are unprotected by a device hardware reset. so ftware reset does not affect the ppb lock bit. the plbwr command can clear the ppb lock bit to 0 to protect the ppb. th ere is no command to set the ppb lock bit therefore the ppb lock bit will remain at 0 until the next power-off or hardware reset. 9.4.7 password protection mode password protection mode allows an even higher level of security than the pers istent sector protection mode, by requiring a 64-bit password for unlocking the ppb lock bit. in addition to this password requirement, after power-up and hardwa re reset, the ppb lock bit is cleare d to 0 to ensure protection at power-up. successful execution of the password unlock command by entering the entire password sets the ppb lock bit to 1, allowing for sector ppb modifications. password protection notes: ? once the password is programmed and verified, the pa ssword mode (aspr[2]=0) mu st be set in order to prevent reading the password. ? the password program command is only capable of programming 0s. programming a 1 after a cell is programmed as a 0 results in the cell left as a 0 with no programming error set. ? the password is all 1s when shipped from spansion. it is located in its own memory space and is accessible through the use of the password program, password read, rdar, and wrar commands. ? all 64-bit password combinations are valid as a password. ? the password mode, once programmed, prevents reading the 64-bit password and further password programming. all further program and read commands to the password region are disabled and these commands are ignored or return undefi ned data. there is no means to veri fy what the password is after the password mode lock bit is selected. password verifica tion is only allowed before selecting the password protection mode. ? the protection mode lock bits are not erasable. table 9.3 sector protection states protection bit values sector state ppb lock ppb dyb 1 1 1 unprotected ? ppb and dyb are changeable. 1 1 0 protected ? ppb and dyb are changeable. 1 0 1 protected ? ppb and dyb are changeable. 1 0 0 protected ? ppb and dyb are changeable. 0 1 1 unprotected ? ppb not changeable, dyb is changeable. 0 1 0 protected ? ppb not changeable, dyb is changeable. 0 0 1 protected ? ppb not changeable, dyb is changeable. 0 0 0 protected ? ppb not changeable, dyb is changeable.
84 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) ? the exact password must be entered in order for the unlocking function to occur. if the password unlock command provided password does not match the hidden internal password, the unlock operation fails in the same manner as a programming operation on a protec ted sector. the p_err bit is set to 1, the wip bit remains set, and the ppb lock bit remains cleared to 0. ? the password unlock command cannot be accepted any faster than once every 100 s 20 s. this makes it take an unreasonably long time (58 million years) for a hacker to run through all the 64-bit combinations in an attempt to correctly match a password. the read status register 1 command may be used to read the wip bit to determine when the devi ce has completed the password unlock command or is ready to accept a new password command. when a valid password is provided the password unlock command does not insert the 100 s delay before returning the wip bit to 0. ? if the password is lost after se lecting the password mode, there is no way to set the ppb lock bit. 9.5 recommended protection process during system manufacture, the flash devi ce configuration should be defined by: 1. programming the otp configuration bits in cr1nv[5, 3:2], cr2nv, cr3nv, and cr4nv as desired. 2. program the secure silicon region (otp area) as desired. 3. program the ppb bits as desired via the ppbp command. 4. program the non-volatile data learning pattern (nvdlr) if it will be used in ddr read commands. 5. program the password register (pass) if password protection will be used. 6. program the asp register as de sired, including the selection of the persistent or password asp protection mode in aspr[2:1]. it is very important to explicitly sele ct a protection mode so that later accidental or malicious programming of the asp regi ster and otp configurati on is preven ted. this is to ensure that only the intended otp prot ection and configuration features are enabled. during system power-up and boot code execution: 1. trusted boot code can determine whether there is any need to program additional ssr (otp area) information. if no ssr changes are needed the freeze bit (cr1v[0]) can be set to 1 to protect the ssr from changes during th e remainder of normal system op eration while power remains on. 2. if the persistent protection mode is in use, tr usted boot code can determine whether there is any need to modify the persistent (ppb) sector protection via th e ppbp or ppbe commands. if no ppb changes are needed the ppblock bi t can be cleared to 0 via t he ppbl to protect the ppb bits from changes during the remainder of normal system operation while power remains on. 3. the dynamic (dyb) sector protection bits can be written as desired via the dybar.
november 6, 2013 s25fs-s_00_04 s25fs-s family 85 data sheet (preliminary) 10. commands all communication between th e host system and s25fs-s family memory devices is in the form of units called commands. all commands begin with an instruction that selects the ty pe of information transfer or device operation to be performed. commands may also have an address, instruct ion modifier, latency period, data transfer to the memory, or data transfer from the memory. all instru ction, address, and data information is transferred sequentially between the host system and memory device. command protocols are also classified by a numerical nomenclature using three numbers to reference the transfer width of three command phases: ? instruction; ? address and instruction modifier (mode); ? data. single bit wide commands start with an instruction and ma y provide an address or data, all sent only on the si signal. data may be sent back to the host serially on the so signal. this is referenced as a 1-1-1 command protocol for single bit width instruction, singl e bit width address and modifier, single bit data. dual or quad input / output (i/o) commands provide an address sent from the host as bit pairs on io0 and io1 or, four bit (nibble) groups on io0, io1, io2, and io3. data is returned to the host similarly as bit pairs on io0 and io1 or, four bit (nibble) groups on io0, io1, io 2, and io3. this is referenced as 1-2-2 for dual i/o and 1-4-4 for quad i/o command protocols. the s25fs-s family also supports a qpi mode in which all information is transferred in 4-bit width, including the instruction, address, modifier, and data. th is is referenced as a 4-4-4 command protocol. commands are structured as follows: ? each command begins with an eight bit (byte) instruction. however, some read commands are modified by a prior read command, such that the instruction is implied from the earlier command. this is called continuous read mode. when the device is in cont inuous read mode, the in struction bits are not transmitted at the beginning of the command because the instruction is the sa me as the read command that initiated the continuous read mode. in contin uous read mode the command will begin with the read address. thus, continuous read mode removes eight inst ruction bits from each read command in a series of same type read commands. ? the instruction may be stand alone or may be followed by address bits to select a location within one of several address spaces in the device. the address may be either a 24-bit or 32-bit, byte boundary, address. ? the serial peripheral interface with multiple io pr ovides the option for each transfer of address and data information to be done one, two, or four bits in parallel. this enables a trade off between the number of signal connections (io bus width) and the speed of information transfer. if the host system can support a two or four bit wide io bus the memory performance can be increased by usi ng the instructions that provide parallel 2-bit (dual) or parallel 4-bit (quad) transfers. ? in legacy spi multiple io mode, the width of all transfers following the instruction are determined by the instruction sent. following transfers may continue to be si ngle bit serial on only the si or serial output (so) signals, they may be done in two bit groups per (dual) transfer on the io0 and io1 signals, or they may be done in 4-bit groups per (quad) transfer on the io0-io3 signals. within the dual or quad groups the least significant bit is on io0. more significant bits are pl aced in significance order on each higher numbered io signal. single bits or parallel bit groups are tran sferred in most to least significant bit order. ? in qpi mode, the width of all transfers, including inst ructions, is a 4-bit wide (quad) transfer on the io0-io3 signals. ? dual i/o and quad i/o read instructions send an instruction modifier called mode bits, following the address, to indicate that the next command will be of t he same type with an implied, rather than an explicit, instruction. the next command thus does not prov ide an instruction byte, only a new address and mode bits. this reduces the time needed to send each command when the same command type is repeated in a sequence of commands. ? the address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before read data is returned to the host.
86 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) ? read latency may be zero to several sck cycles (also referred to as dummy cycles). ? all instruction, address, mode, and data information is transferred in byte granularity. addresses are shifted into the device with the most significant byte first. a ll data is transferred with t he lowest address byte sent first. following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments. ? all attempts to read the flash memory array duri ng a program, erase, or a write cycle (embedded operations) are ignored. the embedded operation will c ontinue to execute without any affect. a very limited set of commands are accepted during an embedded operation. these are discussed in the individual command descriptions. while a program, eras e, or write operation is in progress, it is recommended to check that the write-in progress (w ip) bit is 0 before issuing most commands to the device, to ensure the new command can be accepted. ? depending on the command, the time for execution varies. a command to read status information from an executing command is available to determine when the command completes execution and whether the command was successful. ? although host software in some cases is used to di rectly control the spi interface signals, the hardware interfaces of the host system and the memory device generally handle the details of signal relationships and timing. for this reason, signal relationships and timing are not covered in detail within this software interface focused section of the docu ment. instead, the focus is on the l ogical sequence of bits transferred in each command rather than the signal timing and relationships. following are some general signal relationship descriptions to keep in mind. for additional information on the bit level format and signal timing relationships of commands, see command protocol on page 24 . ? the host always controls the chip select (cs#), serial clock (sck), and serial in put (si) - si for single bit wide transfers. the memory drives serial out put (so) for single bit read transfers. the host and memory alternately drive the io0-io3 signa ls during dual and quad transfers. ? all commands begin with the host selecting the memory by driving cs# low before the first rising edge of sck. cs# is kept low thro ughout a command and when cs# is returned high the command ends. generally, cs# remains low for eight bit transfer mu ltiples to transfer byte granularity information. some commands will not be accepted if cs# is returned high not at an 8-bit boundary.
november 6, 2013 s25fs-s_00_04 s25fs-s family 87 data sheet (preliminary) 10.1 command set summary 10.1.1 extended addressing to accommodate addressing above 128 mb, there are two options: 1. instructions that always require a 4-byte address, used to access up to 32 gb of memory: 2. a 4-byte address mode for backward compatibility to the 3-byte address instructions. the standard 3-byte instructions can be used in conjunction with a 4-byte address mode controlled by the address length configuration bit (cr2v[7]). t he default value of cr2v[7] is loaded from cr2nv[7] (following power-up, hardware reset, or software reset), to enable default 3-byte (24-bit) or 4-byte (32-bit) addressing. when the address length (cr2v[7]) set to 1, the legacy commands are changed to require 4-bytes (32-bits) for the address field. the following instructions can be used in conjunction with the 4-byte address mode conf iguration to switch from 3 bytes to 4 bytes of address field. command name function instruction (hex) 4read read 13 4fast_read read fast 0c 4dior dual i/o read bc 4qior quad i/o read ec 4ddrqior ddr quad i/o read ee 4pp page program 12 4p4e parameter 4-kb erase 21 4se erase 64/256 kb dc 4dybrd dyb read e0 4dybwr dybwr e1 4ppbrd ppb read e2 4ppbp ppb program e3 command name function instruction (hex) read read 03 fast_read read fast 0b dior dual i/o read bb qior quad i/o read eb ddrqior ddr quad i/o read) ed pp page program 02 p4e parameter 4-kb erase 20 se erase 64 / 256 kb d8 rdar read any register 65 wrar write any register 71 ees evaluate erase status d0 otpp otp program 42 otpr otp read 4b dybrd dyb read fa dybwr dybwr fb ppbrd ppb read fc ppbp ppb program fd
88 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 10.1.2 command summary by function table 10.1 s25fs-s family command set (sorte d by function) (sheet 1 of 2) function command name command description instruction value (hex) maximum frequency (mhz) address length (bytes) qpi read device id rdid read id (jedec manufacturer id and jedec cfi) 9f 133 0 yes rsfdp read jedec serial flash discoverable parameters 5a 50 3 yes rdqid read quad id af 133 0 yes register access rdsr1 read status register 1 05 133 0 yes rdsr2 read status register 2 07 133 0 no rdcr read configuration register 1 35 133 0 no rdar read any register 65 133 3 or 4 yes wrr write register (status 1, configuration 1) 01 133 0 yes wrdi write disable 04 133 0 yes wren write enable 06 133 0 yes wrar write any register 71 133 3 or 4 yes clsr clear status register 1 - erase/prog. fail reset this command may be disabled and the instruction value instead used for a program / erase resume command - see configuration register 3 on page 69 30 133 0 yes clsr clear status register 1 (alternate instruction) - erase/prog. fail reset 82 133 0 yes 4bam enter 4-byte address mode b7 133 0 no sbl set burst length c0 133 0 no ees evaluate erase status d0 133 3 or 4 yes dlprd data learning pattern read 41 133 0 no pnvdlr program nv data learning register 43 133 0 no wvdlr write volatile data learning register 4a 133 0 no read flash array read read 03 50 3 or 4 no 4read read 13 50 4 no fast_read fast read 0b 133 3 or 4 no 4fast_read fast read 0c 133 4 no dior dual i/o read bb 66 3 or 4 no 4dior dual i/o read bc 66 4 no qior quad i/o read eb 133 3 or 4 yes 4qior quad i/o read ec 133 4 yes ddrqior ddr quad i/o read ed 80 3 or 4 yes 4ddrqior ddr quad i/o read ee 80 4 yes program flash array pp page program 02 133 3 or 4 yes 4pp page program 12 133 4 yes erase flash array p4e parameter 4-kb sector erase 20 133 3 or 4 yes 4p4e parameter 4-kb sector erase 21 133 4 yes se erase 64 kb or 256 kb d8 133 3 or 4 yes 4se erase 64 kb or 256 kb dc 133 4 yes be bulk erase 60 133 0 yes be bulk erase (alternate instruction) c7 133 0 yes
november 6, 2013 s25fs-s_00_04 s25fs-s family 89 data sheet (preliminary) note: 1. commands not supported in qpi mode have undefined behavior if sent when the device is in qpi mode. 10.1.3 read device identification there are multiple commands to read information ab out the device manufacturer, device type, and device features. spi memories from diffe rent vendors have used different commands and formats for reading information about the memories. the s25fs-s family supports the three device information commands. 10.1.4 register read or write there are multiple registers for reporting embedded op eration status or contro lling device configuration options. there are commands for reading or writing these registers. regi sters contain both volatile and non- volatile bits. non-volatile bits in registers are automatically erased and programmed as a single (write) operation. erase /program suspend /resume eps erase / program suspend 75 133 0 yes eps erase / program suspend (alternate instruction) 85 133 0 yes eps erase / program suspend (alternate instruction) b0 133 0 yes epr erase / program resume 7a 133 0 yes epr erase / program resume (alternate instruction) 8a 133 0 yes epr erase / program resume (alternate instruction) this command may be disabled and the instruction value instead used for a clear status command - see configuration register 3 on page 69 30 133 0 yes one-time program array otpp otp program 42 133 3 or 4 no otpr otp read 4b 133 3 or 4 no advanced sector protection dybrd dyb read fa 133 3 or 4 yes 4dybrd dyb read e0 133 4 yes dybwr dyb write fb 133 3 or 4 yes 4dybwr dyb write e1 133 4 yes ppbrd ppb read fc 133 3 or 4 no 4ppbrd ppb read e2 133 4 no ppbp ppb program fd 133 3 or 4 no 4ppbp ppb program e3 133 4 no ppbe ppb erase e4 133 0 no asprd asp read 2b 133 0 no aspp asp program 2f 133 0 no plbrd ppb lock bit read a7 133 0 no plbwr ppb lock bit write a6 133 0 no passrd password read e7 133 0 no passp password program e8 133 0 no passu password unlock e9 133 0 no reset rsten software reset enable 66 133 0 yes rst software reset 99 133 0 yes reset legacy software reset f0 133 0 no mbr mode bit reset ff 133 0 yes table 10.1 s25fs-s family command set (sorte d by function) (sheet 2 of 2) function command name command description instruction value (hex) maximum frequency (mhz) address length (bytes) qpi
90 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 10.1.4.1 monitoring operation status the host system can determine when a write, program, erase, suspend or other embedded operation is complete by monitoring the writ e-in-progress (wip) bit in the status register. the read from status register 1 command or read any register command provides the state of the wip bit. the program error (p_err) and erase error (e_err) bi ts in the status regist er indicate whether the most recent program or erase command has not completed successfully. when p_ err or e_err bits are set to 1, the wip bit will remain set to one indicating the device remains busy and unable to receive most new operation commands. only status read (rdsr1 05h), read any register (rdar 65h), status clear (clsr 30h or 82h), and software reset (rsten 66h, rst 99h or reset f0h) are valid commands when p_err or e_err is set to 1. a clear status register (clsr) followed by a writ e disable (wrdi) command must be sent to return the device to standby state. clear status register clears the wip, p_err, and e_err bits. wrdi clears the wel bit. alternatively, hardware rese t, or software reset (rst or reset) may be used to return the device to standby state. 10.1.4.2 configuration there are commands to read, write, an d protect registers that control inte rface path width, interface timing, interface address length, and so me aspects of data protection. 10.1.5 read flash array data may be read from the memory starting at any byte boundary. data bytes are sequentially read from incrementally higher byte addresses until the host ends th e data transfer by driving cs # input high. if the byte address reaches the maximum address of the memory a rray, the read will continue at address zero of the array. there are several different read comm ands to specify different access la tency and data path widths. double data rate (ddr) commands also define the addre ss and data bit relationship to both sck edges: ? the read command provides a single address bit per sck rising edge on the si signal with read data returning a single bit per sck falling edge on the so signal. this command has zero latency between the address and the returning data but is limited to a maximum sck rate of 50mhz. ? other read commands have a latency period between the address and returning data but can operate at higher sck frequencies. the latency depends on a configuration register read latency value. ? the fast read command provides a single address bit per sck rising edge on the si signal with read data returning a single bit per sck falling edge on the so signal. ? dual or quad i/o read commands provide address two bi ts or four bits per sck rising edge with read data returning two bits, or four bits of data per sck falling edge on the io0-io3 signals. ? quad double data rate read commands provide address four bits per every sck edge with read data returning four bits of data per every sck edge on the io0-io3 signals. 10.1.6 program flash array programming data requires two commands: write e nable (wren), and page program (pp). the page program command accepts from 1 byte up to 256 or 512 consecutive bytes of data (page) to be programmed in one operation. programming means that bits can eit her be left at 1, or programmed from 1 to 0. changing bits from 0 to 1 requires an erase operation. 10.1.7 erase flash array the parameter sector erase, sector erase, or bulk eras e commands set all the bits in a sector or the entire memory array to 1. a bit needs to be first erased to 1 before programming can change it to a 0. while bits can be individually programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide or array- wide (bulk) level. the write enable (wren) command must precede an erase command.
november 6, 2013 s25fs-s_00_04 s25fs-s family 91 data sheet (preliminary) 10.1.8 otp, block protection, and advanced sector protection there are commands to read and program a separate one-time programmable (otp) array for permanent data such as a serial number. there are commands to control a contiguous group (block) of flash memory array sectors that are protected from program and er ase operations. there are commands to control which individual flash memory array sectors are protected from progra m and erase operations. 10.1.9 reset there are commands to reset to the default conditions present after power-on to the device. however, the software reset command s do not affect the curren t state of the freeze or ppb lock bits. in all other respects a software reset is th e same as a hardware reset. there is a command to reset (exit from) the continuous read mode. 10.1.10 reserved some instructions are reserved for future use. in this generation of the s25fs-s family some of these command instructions may be unused and not affect devi ce operation, some may have undefined results. some commands are reserved to ensure that a legacy or alternate source device command is allowed without effect. this allows legacy software to issue some commands that are not relevant for the current generation s25fs-s family with the assurance thes e commands do not cause some unexpected action. some commands are reserved for use in special versions of the fs-s not addressed by this document or for a future generation. this allows new host memory cont roller designs to plan the flexibility to issue these command instructions. the command format is defined if known at the time this document revision is published. 10.2 identification commands 10.2.1 read identific ation (rdid 9fh) the read identification (rdid) comm and provides read access to manufacturer identification, device identification, and common flash interface (cfi) info rmation. the manufacturer identification is assigned by jedec. the cfi structure is defined by jedec standard. the device identification and cfi values are assigned by spansion. the jedec common flash interface (cfi) specification def ines a device information structure, which allows a vendor-specified software flash managem ent program (driver) to be used for entire families of flash devices. software support can then be device-independent , jedec manufacturer id independent, forward and backward-compatible for the specifie d flash device families. system ve ndors can standardize their flash drivers for long-term software compatibility by using the cfi values to configure a fa mily driver from the cfi information of the device in use. any rdid command issued while a program, erase, or writ e cycle is in progress is ignored and has no effect on execution of the program, erase, or write cycle that is in progress. the rdid instruction is shifte d on si. after the last bit of the rdid instru ction is shifted into the device, a byte of manufacturer identification, two bytes of device identification, extended devic e identification, and cfi information will be shifted sequentially out on so. as a whole this information is referred to as id-cfi. see device id and common flash interface (id-cfi) address map on page 143 for the detail description of the id-cfi contents. continued shifting of output beyond the end of the defin ed id-cfi address space will provide undefined data. the rdid command sequence is termina ted by driving cs# to the logi c high state anytime during data output. the maximum clock frequency for the rdid command is 133 mhz.
92 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) figure 10.1 read identification (rdid) command sequence this command is also supported in qpi mode. in qpi mode the instruction is shifted in on io0-io3 and the returning data is shifted out on io0-io3. figure 10.2 read identification (rdid) qpi mode command 10.2.2 read quad identi fication (rdqid afh) the read quad identification (rdqid) command provides read access to manufacturer identificati on, device identification, and common flash interface (cfi) info rmation. this command is an alternate way of reading the same information provided by the rdid command whil e in qpi mode. in all other respects the command behaves the same as the rdid command. the command is recognized only when the device is in qp i mode (cr2v[6]=1). the in struction is shifted in on io0-io3. after the last bit of the instruction is shift ed into the device, a byte of manufacturer identification, two bytes of device identification, extended device identification, and cfi information will be shifted sequentially out on io0-io3. as a whole this information is referred to as id-cfi. see device id and common flash interface (id-cfi) address map on page 143 for the detail description of the id-cfi contents. continued shifting of output beyond the end of the defin ed id-cfi address space will provide undefined data. the command sequence is terminated by driving cs# to the logic high state anytime during data output. the maximum clock frequency for the command is 133 mhz. figure 10.3 read quad identification (rdqid) command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction data 1 data n cs# sclk io0 io1 io2 io3 phase 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 instruction d1 d2 d3 d4 d5 cs# sclk io0 io1 io2 io3 phase 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 instruction d1 d2 d3 d4 d5
november 6, 2013 s25fs-s_00_04 s25fs-s family 93 data sheet (preliminary) 10.2.3 read serial fl ash discoverable parameters (rsfdp 5ah) the command is initiated by shifting on si the inst ruction code ?5ah?, followed by a 24-bit address of 000000h, followed by 8 dummy cycles. th e sfdp bytes are then shifted out on so starting at the fallin g edge of sck after the dummy cycles. the sfdp bytes are al ways shifted out with the msb first. if the 24-bit address is set to any other value, the selected location in the sfdp space is the starting point of the data read. this enables random access to any parameter in the sfdp space. the rsfdp command is supported up to 50 mhz. figure 10.4 rsfdp command sequence this command is also supported in qpi mode. in qpi mode the instruction is shifted in on io0-io3 and the returning data is shifted out on io0-io3. figure 10.5 rsfdp qpi mode command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1 cs# sclk io0 io1 io2 io3 phase 4 0 20 4 0 4 0 4 0 4 0 4 0 5 1 21 5 1 5 1 5 1 5 1 5 1 6 2 22 6 2 6 2 6 2 6 2 6 2 7 3 23 7 3 7 3 7 3 7 3 7 3 instruct. address dummy d1 d2 d3 d4
94 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 10.3 register access commands 10.3.1 read status regi ster 1 (rdsr1 05h) the read status register 1 (rdsr1 ) command allows the status register 1 contents to be read from so. the volatile version of st atus register 1 (sr1v) contents may be read at any time, even while a program, erase, or write operation is in progr ess. it is possible to read status register 1 continuously by providing multiples of eight clock cycles. the status is updated for each eight cycle read. the maximum clock frequency for the rdsr1 (05h) command is 133 mhz. figure 10.6 read status register 1 (rdsr1) command sequence this command is also supported in qpi mode. in qpi mode the instruction is shifted in on io0-io3 and the returning data is shifted out on io 0-io3, two clock cycles per byte. figure 10.7 read status register 1 (rdsr1) qpi mode command 10.3.2 read status regi ster 2 (rdsr2 07h) the read status register 2 (rdsr2 ) command allows the status register 2 contents to be read from so. the status register 2 contents may be read at any time , even while a program, erase, or write operation is in progress. it is possible to read the status register 2 continu ously by providing multiples of eight clock cycles. the status is updated fo r each eight cycle read. th e maximum clock frequency fo r the rdsr2 command is 133 mhz. figure 10.8 read status register 2 (rdsr2) command in qpi mode, status register 2 may be re ad via the read any register command, see read any register (rdar 65h) on page 101 cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction status updated status cs# sclk io0 io1 io2 io3 phase 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 instruct. d1 d2 d3 d4 d5 cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction status updated status
november 6, 2013 s25fs-s_00_04 s25fs-s family 95 data sheet (preliminary) 10.3.3 read configurati on register (rdcr 35h) the read configuration register (rdcr) command allo ws the volatile configuration register (cr1v) contents to be read from so. it is possible to read cr1v continuously by providing multiples of eight clock cycles. the configuration register contents may be read at any time , even while a progra m, erase, or write operation is in progress. figure 10.9 read configuration register (rdcr) command sequence in qpi mode, configuration register 1 may be read via the read any register command, see section 10.3.12, read any register (rdar 65h) on page 101 10.3.4 write regi sters (wrr 01h) the write registers (wrr) command allows new values to be written to both the status register 1 and configuration register 1. before the write registers (wrr) command can be accepted by the device, a write enable (wren) command must be received. after the write enable (wren) command has been decoded successfully, the device will set the write enable latch (wel) in the status register to enable any write operations. the write registers (wrr) command is entered by shif ting the instruction and the data bytes on si. the status register is one data byte in length. the wrr operation first erases the register then prog rams the new value as a single operation. the write registers (wrr) command will set the p_err or e_err bits if there is a failure in the wrr operation. see status register 1 volatile (sr1v) on page 61 for a description of the error bits. any status or configuration register bit reserved for the future must be written as a 0. cs# must be driven to the logic high st ate after the eighth or sixteenth bit of data has been latc hed. if not, the write registers (wrr) command is not executed. if cs# is driven high after the eighth cycle then only the status register 1 is written; otherwis e, after the sixteenth cycl e both the status and configuratio n registers are written. as soon as cs# is driven to the logic high state, the self-timed write registers (w rr) operation is initiated. while the write registers (wrr) operation is in progre ss, the status register ma y still be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bi t is a 1 during the self-timed write registers (wrr) operation, and is a 0 when it is co mpleted. when the write registers (wrr) operation is completed, the write enable latch (wel) is set to a 0. the maximum clock frequency for the wrr command is 133 mhz. this command is also supported in qpi mode. in qpi mode the instruction and data is shifted in on io0-io3, two clock cycles per byte. figure 10.10 write registers (wrr) command sequence ? 8-data bits cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction register read repeat register read cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input status register 1
96 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) figure 10.11 write registers (wrr) command sequence ? 16-data bits figure 10.12 write registers (wrr) command sequence ? 16-data bits qpi mode the write registers (wrr) command allows the user to change the values of the block protect (bp2, bp1, and bp0) bits in either the non-volatile status register 1 or in the volatile status register 1, to define the size of the area that is to be treated as read-only. the bpnv_o bit (cr1nv[3]) controls whether wrr writes the non-volatile or volatile version of status regist er 1. when cr1nv[3]=0 wrr writes sr1nv[4:2]. when cr1nv[3]=1 wrr writes sr1v[4:2]. the write registers (wrr) command also allows the user to set the status register write disable (srwd) bit to a 1 or a 0. the status regi ster write disable (srwd) bit and write protect (wp#) signal allow the bp bits to be hardware protected. when the status register write disable (s rwd) bit of the status register is a 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (w el) bit has previously been set by a write enable (wren) command, regardless of the whether write protect (wp#) signal is driven to the logic high or logic low state. when the status register writ e disable (srwd) bit of the status register is set to a 1, two cases need to be considered, depending on the st ate of write protect (wp#): ? if write protect (wp#) signal is driven to the logic hi gh state, it is possible to write to the status and configuration registers provided that the write enable latch (wel) bit has previously been set to a 1 by initiating a write enable (wren) command. ? if write protect (wp#) signal is driven to the logic low state, it is not possible to write to the status and configuration registers even if the write enable latch (wel) bit has previously been set to a 1 by a write enable (wren) command. attempts to write to the st atus and configuration r egisters are rejected, not accepted for execution, and no error indication is provided. as a consequence, all the data bytes in the memory area that are protected by the block protect (bp2, bp1, bp0) bits of the status register, are also hardware protected by wp#. the wp# hardware protection can be provided: ? by setting the status register write disable (srwd) bi t after driving write protect (wp#) signal to the logic low state; ? or by driving write protect (wp#) signal to the logic lo w state after setting the status register write disable (srwd) bit to a 1. the only way to release the hardware protection is to pull the write protect (wp#) signal to the logic high state. if wp# is permanently tied high, hardware protection of the bp bits can never be activated. cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input status register 1 input configuration register 1 cs# sclk io0 io1 io2 io3 phase 4 0 4 0 4 0 5 1 5 1 5 1 6 2 6 2 6 2 7 3 7 3 7 3 instruct. input status input config
november 6, 2013 s25fs-s_00_04 s25fs-s family 97 data sheet (preliminary) notes: 1. the status register originally shows 00h when the de vice is first shipped from spansion to the customer. 2. hardware protection is disabled when quad mode is enabled (cr1 v[1] = 1). wp# becomes io2; therefore, it cannot be utilized. 10.3.5 write en able (wren 06h) the write enable (wren) command sets the write en able latch (wel) bit of the status register 1 (sr1v[1]) to a 0. the write enable latch (wel) bit must be set to a 1 by issuing the write enable (wren) command to enable write, program and erase commands. cs# must be driven into the logic high state after the ei ghth bit of the instruction byte has been latched in on si. without cs# being driven to the logic high state afte r the eighth bit of the instruction byte has been latched in on si, the write enable op eration will not be executed. figure 10.13 write enable (wren) command sequence this command is also supported in qpi mode. in qpi mo de the instruction is shifted in on io0-io3, two clock cycles per byte. figure 10.14 write enable (wren) command sequence qpi mode table 10.2 block protection modes wp# srwd bit mode write protection of registers memory content protected area unprotected area 11 software protected status and configuration registers are writable (if wren command has set the wel bit). the values in the srwd, bp2, bp1, and bp0 bits and those in the configuration register can be changed. protected against page program, sector erase, and bulk erase. ready to accept page program, and sector erase commands. 10 00 01 hardware protected status and configuration registers are hardware write protected. the values in the srwd, bp2, bp1, and bp0 bits and those in the configuration register cannot be changed. protected against page program, sector erase, and bulk erase. ready to accept page program or erase commands. cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction
98 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 10.3.6 write di sable (wrdi 04h) the write disable (wrdi) command cl ears the write enable latch (wel ) bit of the status register 1 (sr1v[1]) to a 1. the write enable latch (wel) bit may be cleared to a 0 by issuing the write disable (wrdi) command to disable page program (pp), sector erase (se), bulk erase (be), write registers (wrr or wrar), otp program (otpp), and other commands, that require wel be set to 1 for execution. the wrdi command can be used by the user to protect memory areas against inad vertent writes that can possibly corrupt the contents of the memory. the wrdi command is ignored during an embedded operation while wip bit =1. cs# must be driven into the logic high state after the ei ghth bit of the instruction byte has been latched in on si. without cs# being driven to the logic high state afte r the eighth bit of the instruction byte has been latched in on si, the write disable operation will not be executed. figure 10.15 write disable (wrdi) command sequence this command is also supported in qpi mode. in qpi mo de the instruction is shifted in on io0-io3, two clock cycles per byte. figure 10.16 write disable (wrdi) command sequence qpi mode cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction
november 6, 2013 s25fs-s_00_04 s25fs-s family 99 data sheet (preliminary) 10.3.7 clear status regi ster (clsr 30h or 82h) the clear status register command resets bit sr1v[5 ] (erase fail flag) and bit sr1v[6] (program fail flag). it is not necessary to set the wel bit before a clear status register comm and is executed. the clear status register command will be accepted even when the device remains busy with wip set to 1, as the device does remain busy when either error bit is set. the wel bit will be unchanged after this command is executed. the legacy clear status register (clsr 30h) instru ction may be disabled and the 30h instruction value instead used for a program / erase resume command - see configuration register 3 on page 69 . the clear status register alternate instruction (clsr 82h) is always available to clear the status register. figure 10.17 clear status register (clsr) command sequence this command is also supported in qpi mode. in qpi mo de the instruction is shifted in on io0-io3, two clock cycles per byte. figure 10.18 clear status register (clsr) command sequence qpi mode 10.3.8 program nvdlr (pnvdlr 43h) before the program nvdlr (pnvdlr) command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) command has been decoded successfully, the device will set the write enab le latch (wel) to enable the pnvdlr operation. the pnvdlr command is entered by shifting the instruction and the data byte on si. cs# must be driven to the logic high state after the eighth bit of data has been latched. if not, the pnvdlr command is not executed. as soon as cs# is driven to the logic high state, the self-timed pnvdlr operation is initiated. while the pnvdlr operati on is in progress, the stat us register may be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bit is a 1 during the self-timed pnvdlr cycle, and is a 0. when it is completed. the pnvdlr operation can report a program error in the p_err bit of the status register. when the pnvdlr operation is complete d, the write enable latch (wel) is set to a 0. the maximum clock frequency for the pnvdlr command is 133 mhz. figure 10.19 program nvdlr (pnvdlr) command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data
100 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 10.3.9 write vdlr (wvdlr 4ah) before the write vdlr (wvdlr) command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) command has been decoded successfully, the device will set the write enable latch (wel) to enable wvdlr operation. the wvdlr command is entered by shifting th e instruction and the data byte on si. cs# must be driven to the logic high state after the eighth bit of data has been latched. if not, the wvdlr command is not executed. as s oon as cs# is driven to the logic high state, the wvdlr operation is initiated with no delays. the maximum clock frequency for the pnvdlr command is 133 mhz. figure 10.20 write vdlr (wvdlr) command sequence 10.3.10 data learning pa ttern read (dlprd 41h) the instruction is shifted on si, then the 8-bit dlp is shifted out on so. it is possible to read the dlp continuously by providing multiples of eight clock cycles. the maximum operating clock frequency for the dlprd command is 133 mhz. figure 10.21 dlp read (dlprd) command sequence 10.3.11 enter 4-byte ad dress mode (4bam b7h) the enter 4-byte address mode (4bam) command sets th e volatile address length bit (cr2v[7]) to 1 to change most 3-byte address commands to require 4 b ytes of address. the read sfdp (rsfdp) command is the only 3-byte command that is not affected by th e address length bit. rsfdp is required by the jedec jesd216 standard to always have only 3 bytes of address. a hardware or software reset is required to exit the 4-byte address mode. figure 10.22 enter 4-byte address mode (4bam b7h) command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction register read repeat register read cs# sck si so phase 7 6 5 4 3 2 1 0 instruction
november 6, 2013 s25fs-s_00_04 s25fs-s family 101 data sheet (preliminary) 10.3.12 read any r egister (rdar 65h) the read any register (rdar) command provides a way to read all device registers - non-volatile and volatile. the instruction is followed by a 3- or 4-by te address (depending on the address length configuration cr2v[7], followed by a number of latency (dummy) cycles set by cr2v[3:0]. t hen the selected register contents are returned. if the read acce ss is continued the same addressed register contents are returned until the command is terminated - only one register is read by each rdar command. reading undefined locations provides undefined data. the rdar command may be used during embedded oper ations to read status register 1 (sr1v). the rdar command is not used for reading registers th at act as a window into a larger array: ppbar, and dybar. there are separate commands required to se lect and read the locati on in the array accessed. the rdar command will read invalid data from the pass register locations if the asp password protection mode is selected by programming aspr[2] to 0. table 10.3 register address map byte address (hex) register name description 00000000 sr1nv non-volatile status and configuration registers 00000001 n/a 00000002 cr1nv 00000003 cr2nv 00000004 cr3nv 00000005 cr4nv ... n/a 00000010 nvdlr non-volatile data learning register ... n/a 00000020 pass[7:0] non-volatile password register 00000021 pass[15:8] 00000022 pass[23:16] 00000023 pass[31:24] 00000024 pass[39:32] 00000025 pass[47:40] 00000026 pass[55:48] 00000027 pass[63:56] ... n/a 00000030 aspr[7:0] non-volatile 00000031 aspr[15:8] ... n/a 00800000 sr1v volatile status and configuration registers 00800001 sr2v 00800002 cr1v 00800003 cr2v 00800004 cr3v 00800005 cr4v ... n/a 00800010 vdlr volatile data learning register ... n/a 00800040 ppbl volatile ppb lock register ... n/a
102 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) figure 10.23 read any register read command sequence note: 1. a = msb of address = 23 for address length cr2v[7] = 0, or 31 for cr2v[7]=1 this command is also supported in qpi mode. in qpi mo de the instruction is shifted in on io0-io3, two clock cycles per byte. figure 10.24 read any register, qpi mode, cr2[7] = 0, command sequence figure 10.25 read any register, qpi mode, cr2[7] = 1 command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1 cs# sclk io0 io1 io2 io3 phase 4 0 20 4 0 4 0 4 0 4 0 4 0 5 1 21 5 1 5 1 5 1 5 1 5 1 6 2 22 6 2 6 2 6 2 6 2 6 2 7 3 23 7 3 7 3 7 3 7 3 7 3 instruct. address dummy d1 d2 d3 d4 cs# sclk io0 io1 io2 io3 phase 4 0 28 4 0 4 0 4 0 4 0 4 0 5 1 29 5 1 5 1 5 1 5 1 5 1 6 2 30 6 2 6 2 6 2 6 2 6 2 7 3 31 7 3 7 3 7 3 7 3 7 3 instruct. address dummy d1 d2 d3 d4
november 6, 2013 s25fs-s_00_04 s25fs-s family 103 data sheet (preliminary) 10.3.13 write any register (wrar 71h) the write any register (wrar) command provides a way to write any device register - non-volatile or volatile. the instruction is followed by a 3- or 4-by te address (depending on the address length configuration cr2v[7], followed by one byte of data to write in the address selected register. before the wrar command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the wip bit in sr1v may be c hecked to determine when the operation is completed. the p_err and e_err bits in sr1v may be checked to determine if any error occurred during the operation. some registers have a mixture of bit types and individual rules controlling which bits may be modified. some bits are read only, some are otp. read only bits are never modified and the related bits in the wrar command data byte are ignored without setting a program or erase error indication (p_err or e_ err in sr1v). hence, the value of these bits in the wrar data byte do not matter. otp bits may only be programmed to the level opposite of their default state. writing of otp bits back to their default state is ignored and no error is set. non-volatile bits which are changed by the wrar dat a, require non-volatile register write time (t w) to be updated. the update process involves an erase and a program operation on the non-volatile register bits. if either the erase or program portion of the update fails the related error bit and wip in sr1v will be set to 1. volatile bits which are changed by the wrar dat a, require the volatile register write time (t cs ) to be updated. status register 1 may be repeatedly read (polled) to monitor the write-in-progress (wip) bit (sr1v[0]) and the error bits (sr1v[6,5]) to determine when the register write is completed or failed. if there is a write failure, the clear status command is used to clear the error status and enable the device to return to standby state. however, the ppbl register can not be written by the wrar comm and. only the ppb lock bit write (plbwr) command can write the ppbl register. the command sequence and behavior is the same as the pp or 4pp command with only a single byte of data provided. see section 10.5.2, page program (pp 02h or 4pp 12h) on page 114 . the address map of the register s is the same as shown for section 10.3.12, read any register (rdar 65h) on page 101 . 10.3.14 set burst length (sbl c0h) the set burst length (sbl) command is used to configur e the burst wrap feature. burst wrap is used in conjunction with quad i/o read and ddr quad i/o read, in legacy spi or qpi mode, to access a fixed length and alignment of data. certai n applications can benefit from this feature by improving the overall system code execution performance. t he burst wrap feature a llows applicati ons that use cache, to start filling a cache line with instruction or data from a critical address first, then fill the remainder of the cache line afterwards within a fixed length (8 /16/32/64-bytes) of data, without issuing multiple read commands. the set burst length (sbl) command writes the cr4v regi ster to enable or disabl e the wrapped read feature and set the wrap boundary. when enabled the wrapped read feature changes the related read commands from sequentially reading until the command ends, to r eading sequentially wrapped within a group of bytes. when cr4v[4]=1, the wrap mode is not enabled and unlimited length sequential read is performed. when cr4v[4]=0, the wrap m ode is enabled and a fixed length and aligned group of 8, 16, 32, or 64 bytes is read starting at the byte address provided by the read command and wrapping around at the group alignment boundary. the group of bytes is of length and aligned on an 8-, 16-, 32-, or 64-byte boundary. cr4v[1:0] selects the boundary. see configuration register 4 volatile (cr4v) on page 72 . the starting address of the read command selects th e group of bytes and the first data returned is the addressed byte. bytes are then read sequentially until t he end of the group boundary is reached. if the read continues the address wraps to the beginning of the group and continues to read sequentially. this wrapped read sequence continues until the command is ended by cs# returning high.
104 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) the power-on reset, hardware reset, or software reset default burst length can be changed by programming cr4nv with the desired value using the wrar command. figure 10.26 set burst length command sequence 10.4 read memory array commands read commands for the main flash array provide many options for prior generat ion spi compatibility or enhanced performance spi: ? some commands transfer address or data on each risi ng edge of sck. these are called single data rate commands (sdr). ? some sdr commands transfer address one bit per risi ng edge of sck and return data 1bit of data per rising edge of sck. these are called single width commands. ? some sdr commands transfer both address and data two or four bits per rising edge of sck. these are called dual i/o for two bits, quad i/o, and qpi for four bi ts. qpi also transfers instruction four bits per rising edge. ? some commands transfer address and data on both th e rising edge and falling edge of sck. these are called double data rate (ddr) commands. ? there are ddr commands for 4 bits of address or data per sck edge. these are called quad i/o ddr and qpi ddr for four bit per edge transfer. all of these commands, except qpi read, begin with an instruction code that is transferred one bit per sck rising edge. qpi read transfers the instruction four bi ts per sck rising edge.the instruction is followed by either a 3- or 4-byte address transferred at sdr or ddr. commands transferring address or data 2 or 4 bits per clock edge are called multiple i/o (mio) commands. for s25fs-s family devices at 256-mbits or higher density, the traditional spi 3-byte addresses are unable to directly address all locati ons in the memory array. separate 4-byte address read commands are provided fo r access to the entire address space. these devices may be configured to take a 4-byte address from th e host system with the tr aditional 3-byte address commands. the 4-byte address mode for traditional comman ds is activated by setting the address length bit table 10.4 example burst wrap sequences cr4v[4,1:0] value (hex) wrap boundary (bytes) start address (hex) address sequence (hex) 1x sequential xxxxxx03 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c, 0d, 0e, 0f, 10, 11, 12, 13, 14, 15, 16, 17, 18, ... 00 8 xxxxxx00 00, 01, 02, 03, 04, 05, 06, 07, 00, 01, 02, ... 00 8 xxxxxx07 07, 00, 01, 02, 03, 04, 05, 06, 07, 00, 01, ... 01 16 xxxxxx02 02, 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c, 0d, 0e, 0f, 00, 01, 02, 03, ... 01 16 xxxxxx0c 0c, 0d, 0e, 0f, 00, 01, 02, 03, 02, 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c, 0d, 0e, ... 02 32 xxxxxx0a 0a, 0b, 0c, 0d, 0e, 0f, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c, 0d, 0e, 0f, ... 02 32 xxxxxx1e 1e, 1f, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c, 0d, 0e, 0f, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f, 00, ... 03 64 xxxxxx03 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c, 0d, 0e, 0f, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2a, 2b, 2c, 2d, 2e, 2f, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3a, 3b, 3c, 3d, 3e, 3f, 00, 01, 02 ... 03 64 xxxxxx2e 2e, 2f, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3a, 3b, 3c, 3d, 3e, 3f, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 0a, 0b, 0c, 0d, 0e, 0f, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2a, 2b, 2c, 2d, 2e, 2f, ... cs# sclk si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data
november 6, 2013 s25fs-s_00_04 s25fs-s family 105 data sheet (preliminary) in configuration register 2 to 0. in the fs128s, hig her order address bits above a23 in the 4 byte address commands, or commands using 4-byte address mode ar e not relevant and are ig nored because the flash array is only 128 mbits in size. the quad i/o and qpi commands provide a performanc e improvement option controlled by mode bits that are sent following the address bits. the mode bits indi cate whether the command following the end of the current read will be another read of the same type, without an instruction at the beginning of the read. these mode bits give the option to eliminate the instruction cycles when doing a series of quad read accesses. some commands require delay cycles foll owing the address or mode bits to allow time to access the memory array - read latency. the delay or read latency cycl es are traditionally called dummy cycles. the dummy cycles are ignored by the memory thus any data provided by the host during these cycle s is ?don?t care? and the host may also leave the si signal at high im pedance during the dummy cycles. when mio commands are used the host must stop driving the io signals (outpu ts are high impedance) before the end of last dummy cycle. when ddr comm ands are used the host must not drive t he i/o signals during any dummy cycle. the number of dummy cycles varies with t he sck frequency or performance opti on selected via th e configuration register 2 (cr2v[3:0]) latency code. dummy cycles are measured from sck falling edge to next sck falling edge. spi outputs are traditiona lly driven to a new value on the falling edge of each sck. zero dummy cycles means the returning data is driven by the memory on the same falling edge of sck that the host stops driving address or mode bits. the ddr commands may optionally have an 8-edge data learning pattern (dlp) driven by the memory, on all data outputs, in the dummy cyc les immediately before the start of data. the dlp can help the host memory controller determine the phase shift from sck to data edges so that the memory controller can capture data at the c enter of the data eye. when using sdr i/o commands at higher sck frequencie s (>50 mhz), an lc that provides one or more dummy cycles should be selected to allow additional time for the host to stop drivin g before the memory starts driving data, to minimize i/o driver conflict. when using ddr i/o commands with the dlp enabled, an lc that provides five or more dummy cycles should be selected to allow one cycle of additional time for the host to stop driving before the memory starts driving the 4-cycle dlp. each read command ends when cs# is returned high at any point during data return. cs# must not be returned high during the mode or dummy cycles before data returns as this may cause mode bits to be captured incorrectly; making it indeterminate as to whether the device remains in continuous read mode. 10.4.1 read (read 03h or 4read 13h) the instruction ? 03h (cr2v[7]=0) is followed by a 3-byte address (a23-a0) or ? 03h (cr2v[7]=1) is followed by a 4-byte address (a31-a0) or ? 13h is followed by a 4-byte address (a31-a0) then the memory contents, at the address given, are shifted out on so. the maximum operating clock frequency for the read command is 50 mhz. the address can start at any byte location of the memo ry array. the address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read inst ruction and address 000000h provided. when the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely. figure 10.27 read command sequence (3-byte address, 03h or 13h) note: 1. a = msb of address = 23 for cr2v[7]=0, or 31 for cr2v[7]=1 or command 13h. cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address data 1 data n
106 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 10.4.2 fast read (fast_read 0bh or 4fast_read 0ch) the instruction ? 0bh (cr2v[7]=0) is followed by a 3-byte address (a23-a0) or ? 0bh (cr2v[7]=1) is followed by a 4-byte address (a31-a0) or ? 0ch is followed by a 4-byte address (a31-a0) the address is followed by dummy cycles depending on the latency code set in the configuration register cr2v[3:0]. the dummy cycles allow the device internal circuits addi tional time for a ccessing the initial address location. during the dummy cycles the data value on so is ? don?t care? and may be high impedance. then the memory contents, at the a ddress given, are shifted out on so. the maximum operating clock frequency for fast read command is 133 mhz. the address can start at any byte location of the memo ry array. the address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read inst ruction and address 000000h provided. when the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely. figure 10.28 fast read (fast_read) command sequence (3-byte address, 0bh [cr2v[7]=0) note: 1. a = msb of address = 23 for cr2v[7]=0, or 31 for cr2v[7]=1 or command 0ch. 10.4.3 dual i/o read (d ior bbh or 4dior bch) the instruction ? bbh (cr2v[7]=0) is followed by a 3-byte address (a23-a0) or ? bbh (cr2v[7]=1) is followed by a 4-byte address (a31-a0) or ? bch is followed by a 4-byte address (a31-a0) the dual i/o read commands improve throughput wit h two i/o signals ? io0 (si) and io1 (so). this command takes input of the address and returns read data two bits per sck rising edge. in some applications, the reduced address input and data output ti me might allow for code execution in place (xip) i.e. directly from the memory device. the maximum operating clock frequency for dual i/o read is 133 mhz. the dual i/o read command has continuous read mode bits that follow the address so, a series of dual i/o read commands may eliminate the 8-bit instruction af ter the first dual i/o read command sends a mode bit pattern of axh that indicates the following command will also be a dual i/o read command. the first dual i/o read command in a series starts with the 8-bit instru ction, followed by address, followed by four cycles of mode bits, followed by an optional latency period. if the mode bit pattern is axh the next command is assumed to be an additional dual i/o read command t hat does not provide instru ction bits. that command starts with address, followed by mode bits, followed by optional latency. variable latency may be added after the mode bits are shifted into si and so before data begins shifting out of io0 and io1. this lat ency period (dummy cycles) allows the device internal circuitry enough time to access data at the initial address. during the dummy cycles, the data value on si and so are ?don?t care? and may be high impedance. the number of dummy cycles is det ermined by the frequency of sck. the latency is configured in cr2v[3:0]. the continuous read feature removes the need for the instruction bits in a sequence of read accesses and greatly improves code execution (xip) performance. the upper nibble (bits 7-4) of the mode bits control the cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1
november 6, 2013 s25fs-s_00_04 s25fs-s family 107 data sheet (preliminary) length of the next dual i/o read command through the incl usion or exclusion of the first byte instruction code. the lower nibble (bits 3-0) of the mo de bits are ?don?t care? (?x?) and may be high impedance. if the mode bits equal axh, then the device remains in dual i/o cont inuous read mode and the next address can be entered (after cs# is raised high and then asserted low) wit hout the bbh or bch instruction, as shown in figure 10.31 on page 108 ; thus, eliminating eight cycles of the command sequence. the following sequences will release the device from dual i/o continuous read mode; after which, the device can accept standard spi commands: 1. during the dual i/o continuous read command sequence, if the mode bits are any value other than axh, then the next time cs# is raised high the device will be released from dual i/o con ti no us read mode. 2. send the mode reset command. note that the four mode bit cycles are part of the device?s internal circui try latency time to access the initial address after the last address cycle that is clocked into io0 (si) and io1 (so). it is important that the i/o signals be set to high-impedance at or before the falling edge of the first data out clock. at higher clock speeds the time available to tu rn off the host out puts before the memory device begins to drive (bus turn around) is diminished. it is allowed and may be helpful in preventing i/o signal contention, for the host system to turn off the i/o signal outputs (make them high impedance) during the last two ?don?t care? mode cycles or during any dummy cycles. following the latency period the memory content, at the address given, is shifted out two bits at a time through io0 (si) and io1 (so). two bits are shifted out at the sck frequency at the falling edge of sck signal. the address can start at any byte location of the memo ry array. the address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read inst ruction and address 000000h provided. when the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely. cs# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate. figure 10.29 dual i/o read command sequence (3 -byte address, bbh [cr2v[7]=0]) note: 1. least significant 4 bits of mode are don?t care and it is op tional for the host to drive these bits. the host may turn off dr ive during these cycles to increase bus turn around time between mode bits from host and returning data from the memory. figure 10.30 dual i/o read command sequence (4 -byte address, bbh [cr2v[7]=1]) cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 22 2 0 6 4 2 0 6 4 2 0 6 4 2 0 23 3 1 7 5 3 1 7 5 3 1 7 5 3 1 instruction address mode dum data 1 data 2 cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 30 2 0 6 4 2 0 6 4 2 0 6 4 2 0 31 3 1 7 5 3 1 7 5 3 1 7 5 3 1 instruction address mode dum data 1 data 2
108 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) figure 10.31 dual i/o continuous read command se quence (4-byte address [cr2v[7]=1]) 10.4.4 quad i/o read (qio r ebh or 4qior ech) the instruction ? ebh (cr2v[7]=0) is followed by a 3-byte address (a23-a0) or ? ebh (cr2v[7]=1) is followed by a 4-byte address (a31-a0) or ? ech is followed by a 4-byte address (a31-a0) the quad i/o read command improves throughput with f our i/o signals ? io0-io3. it allows input of the address bits four bits per serial sck clock. in so me applications, the reduced instruction overhead might allow for code execution (xip) directly from s25fs- s family devices. the quad bit of the configuration register must be set (cr1v[1]=1) to enable t he quad capability of s25fs-s family devices. the maximum operating clock frequency for quad i/o read is 133mhz. for the quad i/o read command, there is a latency requir ed after the mode bits (described below) before data begins shifting out of io0-io3. this latency peri od (i.e., dummy cycles) allows the device?s internal circuitry enough time to access data at the initial address. during latency cycles, th e data value on io0-io3 are ?don?t care? and may be high impedance. the numbe r of dummy cycles is determined by the frequency of sck. the latency is configured in cr2v[3:0]. following the latency period, the memory contents at the address given, is shifted out four bits at a time through io0-io3. each nibble (4 bits) is shifted ou t at the sck frequency by the falling edge of the sck signal. the address can start at any byte location of the memo ry array. the address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read inst ruction and address 000000h provided. when the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely. address jumps can be done without the need for additional quad i/o read instructions. this is controlled through the setting of the mode bits (after the address sequence, as shown in figure 10.32 on page 109 or figure 10.35 on page 110 ). this added feature removes the need for the instruction sequence and greatly improves code execution (xip). the upper nibble (bits 7-4) of the mode bits control the length of the next quad i/o instruction through t he inclusion or exclusion of the first byte instruction code. the lower nibble (bits 3-0) of the mode bits are ?don?t care? (?x?). if the mode bits equal axh, then the device remains in quad i/o high performance read mode and the next address can be entered (after cs# is raised high and then asserted low) without requiring the ebh or ech instruction, as shown in figure 10.34 on page 109 or figure 10.36 on page 110 ; thus, eliminatin g eight cycles for the comm and sequence. the following sequences will release the device from quad i/o high performance read mode; afte r which, the device can accept standard spi commands: 1. during the quad i/o read command sequence, if the mode bits are any value other than axh, then the next time cs# is raised high the device will be released from quad i/o high performance read mode. 2. send the mode reset command. note that the two mode bit clock cycl es and additional wait states (i .e., dummy cycles) a llow the device?s internal circuitry latency time to ac cess the initial address a fter the last address cycle t hat is clocked into io0- io3. it is important that the io0-io3 signal s be set to high-impedance at or before the falling edge of the first data out clock. at higher clock speeds the time available to turn off the host outputs before the memory device begins to drive (bus turn around) is diminished. it is allowed and may be helpful in preventing io0-io3 signal cs# sck io0 io1 phase 6 4 2 0 30 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 31 3 1 7 5 3 1 7 5 3 1 7 5 3 1 data n address mode dum data 1 data 2
november 6, 2013 s25fs-s_00_04 s25fs-s family 109 data sheet (preliminary) contention, for the host system to turn off the io0- io3 signal outputs (make them high impedance) during the last ?don?t care? mode cycle or during any dummy cycles. cs# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate. in qpi mode (cr2v[6]=1) the quad i/o instructions are sent 4 bits per sck rising edge. the remainder of the command protocol is identical to the quad i/o commands. figure 10.32 quad i/o read command sequence (3-byte address, ebh [cr2v[7]=0]) figure 10.33 quad i/o read command sequence (3-byte address, ebh [cr2v[7]=0]) qpi mode figure 10.34 continuous quad i/o read comm and sequence (3-byte address) cs# sclk io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 20 4 0 4 0 4 0 4 0 4 0 4 0 21 5 1 5 1 5 1 5 1 5 1 5 1 22 6 2 6 0 6 2 6 2 6 2 6 2 23 7 3 7 1 7 3 7 3 7 3 7 3 instruction address mode dummy d1 d2 d3 d4 cs# sclk io0 io1 io2 io3 phase 4 0 20 4 0 4 4 0 4 0 4 0 4 0 5 1 21 5 1 5 5 1 5 1 5 1 5 1 6 2 22 6 2 6 0 6 2 6 2 6 2 6 2 7 3 23 7 3 7 1 7 3 7 3 7 3 7 3 instruct. address mode dummy d1 d2 d3 d4 cs# sck io0 io1 io2 io3 phase 4 0 4 0 20 4 0 4 0 4 0 4 0 6 4 2 0 5 1 5 1 21 5 1 5 1 5 1 5 1 7 5 3 1 6 2 6 2 22 6 2 6 2 6 2 6 1 7 5 3 1 7 3 7 3 23 7 3 7 3 7 3 7 1 7 5 3 1 dn-1 dn address mode dummy d1 d2 d3 d4
110 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) figure 10.35 quad i/o read command sequence (4-byte address, ech or ebh [cr2v[7]=1]) figure 10.36 continuous quad i/o read comm and sequence (4-byte address) note: 1. the same sequence is used in qpi mode figure 10.37 quad i/o read command sequence (4-byte address, ech or ebh [cr2v[7]=1]) qpi mode cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 28 4 0 4 0 4 0 4 0 4 0 4 0 29 5 1 5 1 5 1 5 1 5 1 5 1 30 6 2 6 0 6 2 6 2 6 2 6 2 31 7 3 7 1 7 3 7 3 7 3 7 3 instruction address mode dummy d1 d2 d3 d4 cs# sck io0 io1 io2 io3 phase 4 0 4 0 28 4 0 4 0 4 0 4 0 6 4 2 0 5 1 5 1 29 5 1 5 1 5 1 5 1 7 5 3 1 6 2 6 2 30 6 2 6 2 6 2 6 1 7 5 3 1 7 3 7 3 31 7 3 7 3 7 3 7 1 7 5 3 1 dn-1 dn address mode dummy d1 d2 d3 d4 cs# sclk io0 io1 io2 io3 phase 4 0 28 4 0 4 4 0 4 0 4 0 4 0 5 1 29 5 1 5 5 1 5 1 5 1 5 1 6 2 30 6 2 6 6 2 6 2 6 2 6 2 7 3 31 7 3 7 7 3 7 3 7 3 7 3 instruct. address mode dummy d1 d2 d3 d4
november 6, 2013 s25fs-s_00_04 s25fs-s family 111 data sheet (preliminary) 10.4.5 ddr quad i /o read (edh, eeh) the ddr quad i/o read command improves throughput with f our i/o signals - io0-io3. it is similar to the quad i/o read command but allows input of the address four bits on every edge of the clock. in some applications, the reduced inst ruction overhead might allow for code ex ecution (xip) directly from s25fs-s family devices. the quad bit of the configuration re gister must be set (cr1v[1]=1) to enable the quad capability. the instruction ? edh (cr2v[7]=0) is followed by a 3-byte address (a23-a0) or ? edh (cr2v[7]=1) is followed by a 4-byte address (a31-a0) or ? eeh is followed by a 4-byte address (a31-a0) the address is followed by mode bits. then the memory c ontents, at the address given, is shifted out, in a ddr fashion, with four bits at a ti me on each clock edge through io0-io3. the maximum operating clock frequency for ddr quad i/o read command is 80 mhz. for ddr quad i/o read, there is a latency required afte r the last address and mode bits are shifted into the io0-io3 signals before data begins sh ifting out of io0-io3. this latenc y period (dummy cycles) allows the device?s internal circuitry enough ti me to access the initia l address. during these latency cycles, the data value on io0-io3 are ?don?t care? and may be high impedance. when the data learning pattern (dlp) is enabled the host system must not drive the io signals during the dummy cycles. the io signals must be left high impedance by the host so that the memory device can drive the dlp during the dummy cycles. the number of dummy cycles is determined by the freque ncy of sck. the latency is configured in cr2v[3:0]. mode bits allow a series of quad i/o ddr commands to el iminate the 8-bit instruction after the first command sends a complementary mode bit pattern, as shown in figure 10.38 and figure 10.40 . this feature removes the need for the 8-bit sdr instruction sequence and dram atically reduces initial access times (improves xip performance). the mode bits control the length of the next ddr quad i/o read operation through the inclusion or exclusion of the first byte instruction code. if the upper nibble (io[7:4]) and lower nibble (io[3:0]) of the mode bits are complementary (i.e. 5h and ah ) the device transitions to continuous ddr quad i/o read mode and the next address can be entered (after cs# is raised high and then asserted low) without requiring the edh or eeh instruction, as shown in figure 10.39 on page 112 and figure 10.42 on page 113 thus, eliminating eight cycles from the command sequence. t he following sequences wi ll release the device from continuous ddr quad i/o read mode; after wh ich, the device can accept standard spi commands: 1. during the ddr quad i/o read command sequence, if the mode bits are not complementary the next time cs# is raised high and then asserted low the device will be released from ddr quad i/o read mode. 2. send the mode reset command. the address can start at any byte location of the memo ry array. the address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. the entire memory can therefore be read out with one single read inst ruction and address 000000h provided. when the highest address is reached, the address counter will wrap around and roll back to 000000h, allowing the read sequence to be continued indefinitely. cs# should not be driven high during mode or dummy bi ts as this may make the mode bits indeterminate. note that the memory devices may drive the ios with a pr eamble prior to the first data value. the preamble is a data learning pattern (dlp) that is used by the ho st controller to optimize data capture at higher frequencies. the preamble drives th e io bus for the four clock cycles i mmediately before data is output. the host must be sure to stop driving the io bus prior to th e time that the memory star ts outputting the preamble. the preamble is intended to give the host controller an indication about the round trip time from when the host drives a clock edge to when the corresponding data value returns from the memory device. the host controller will skew the data capture point during the pr eamble period to optimize timing margins and then use the same skew time to capture the data during the rest of the read operation. the optimized capture point will be determined during the preamble period of every read oper ation. this optimization strategy is intended to compensate for both the pvt (process, voltage, temper ature) of both the memory device and the host controller as well as any syst em level delays caused by flight time on the pcb. although the data learning pattern (dlp) is programma ble, the following example shows example of the dlp of 34h. the dlp 34h (or 00110100) will be driven on eac h of the active outputs (i.e. all four sios). this
112 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) pattern was chosen to cover both ?dc? and ?ac? data transition scenarios. the tw o dc transition scenarios include data low for a long period of time (two half clocks) followed by a high going transition (001) and the complementary low going transition (110). the two ac transition scenarios include data low for a short period of time (one half clock) followed by a high going tr ansition (101) and the complementary low going transition (010). the dc transitions will typically occur with a st arting point closer to the supply rail than the ac transitions that may not have fully settled to their steady state (dc) levels. in many cases the dc transitions will bound the beginning of the data valid period and the ac transitions will bound the ending of the data valid period. these transitions will allow the host controller to identify the beginning and ending of the valid data eye. once the data eye has been characterized t he optimal data capture poi nt can be chosen. see spi ddr data learning registers on page 75 for more details. in qpi mode (cr2v[6]=1) the ddr q uad i/o instructions are sent 4 bits per sck rising edge. the remainder of the command protocol is identi cal to the ddr quad i/o commands. figure 10.38 ddr quad i/o read initial access (3 -byte address, edh [cr2v[7]=0) figure 10.39 continuous ddr quad i/o read subsequent access (3-byte address) figure 10.40 ddr quad i/o read initial access (4-b yte address, eeh or edh [cr2v[7]=1]) note: 1. example dlp of 34h (or 00110100). cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 20 16 12 8 4 0 4 0 7 6 5 4 3 2 1 0 4 0 4 0 21 17 13 9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1 22 18 14 10 6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2 23 19 15 11 7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3 instruction address mode dummy dlp d1 d2 cs# sck io0 io1 io2 io3 phase 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4 0 4 0 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 1 5 1 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 2 6 2 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 3 7 3 address mode dummy d1 d2 d3 d4 d5 cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 28 24 20 16 12 8 4 0 4 0 6 5 4 3 2 1 0 4 0 4 0 29 25 21 17 13 9 5 1 5 1 6 5 4 3 2 1 0 5 1 5 1 30 26 22 18 14 10 6 2 6 2 6 5 4 3 2 1 0 6 2 6 2 31 27 23 19 15 11 7 3 7 3 6 5 4 3 2 1 0 7 3 7 3 instruction address mode dummy dlp d1 d2
november 6, 2013 s25fs-s_00_04 s25fs-s family 113 data sheet (preliminary) figure 10.41 ddr quad i/o read initial access (4-byte address, eeh or edh [cr2v[7]=1]) qpi mode note: 1. example dlp of 34h (or 00110100). figure 10.42 continuous ddr quad i/o read subsequent access (4-byte address) note: 1. example dlp of 34h (or 00110100). 10.5 program flash array commands 10.5.1 program granularity 10.5.1.1 page programming page programming is done by loading a page buffer with data to be programmed and issuing a programming command to move data from the buffer to the memory a rray. this sets an upper limit on the amount of data that can be programmed with a single programming command. page programming allows up to a page size (either 256 or 512 bytes) to be programmed in one operation. the page size is determined by the configuration register bit cr3v[4]. the page is align ed on the page size address boundary. it is possible to program from one bit up to a page size in each p age programming operation. it is recommended that a multiple of 16-byte length and aligned program bloc ks be written. for the very best performance, programming should be done in full pages of 512 by tes aligned on 512-byte boundaries with each page being programmed only once. 10.5.1.2 single byte programming single byte programming allows full backward compatibility to the legacy standard spi page programming (pp) command by allowing a single byte to be programmed anywhere in the memory array. cs# sclk io0 io1 io2 io3 phase 4 0 28 24 20 16 12 8 4 0 4 0 7 6 5 4 3 2 1 0 4 0 4 0 5 1 29 25 21 17 13 9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1 6 2 30 26 22 18 14 10 6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2 7 3 31 27 23 19 15 11 7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3 instruct. address mode dummy dlp d1 d2 cs# sck io0 io1 io2 io3 phase 28 24 20 16 12 8 4 0 4 0 6 5 4 3 2 1 0 4 0 4 0 4 29 25 21 17 13 9 5 1 5 1 6 5 4 3 2 1 0 5 1 5 1 5 30 26 22 18 14 10 6 2 6 2 6 5 4 3 2 1 0 6 2 6 2 6 31 27 23 19 15 11 7 3 7 3 6 5 4 3 2 1 0 7 3 7 3 7 address mode dummy dlp d1 d2
114 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 10.5.2 page program (pp 02h or 4pp 12h) the page program (pp) command allows bytes to be pr ogrammed in the memory (changing bits from 1 to 0). before the page program (pp) commands can be accept ed by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) command has been decoded successfully, the device sets the write enable latch (wel) in the status register to enable any write operations. the instruction ? 02h (cr2v[7]=0) is followed by a 3-byte address (a23-a0) or ? 02h (cr2v[7]=1) is followed by a 4-byte address (a31-a0) or ? 12h is followed by a 4-byte address (a31-a0) and at least one data byte on si. depending on cr3v[4], t he page size can either be 256 or 512 bytes. up to a page can be provided on si after the 3-byte address wit h instruction 02h or 4-by te address with instruction 12h has been provided. if more data is sent to the device than the space between the starting address and the page aligned end boundary, the data loading sequence will wrap from the last byte in the page to the zero byte location of the same page and begin overwriting any data previously loaded in the page. the la st page worth of data is programmed in the page. this is a re sult of the device being equipped wit h a page program buffer that is only page size in length. if less than a page of data is se nt to the device, these data bytes will be programmed in sequence, starting at the provided address within the page, without having an y affect on the other bytes of the same page. using the page program (pp) command to load an ent ire page, within the page boundary, will save overall programming time versus loading less than a page into the program buffer. the programming process is managed by the flash memory device internal control logic. after a programming command is issued, the programming operation status ca n be checked using the read status register 1 command. the wip bit (sr1v[0]) will indicate when the programming operation is completed. the p_err bit (sr1v[6]) will indicate if an error occurs in the prog ramming operation that prev ents successful completion of programming. this includes attempt ed programming of a protected area. figure 10.43 page program (pp 02h or 4pp 12h) command sequence note: 1. a = msb of address = a23 for pp 02h, or a31 for 4pp 12h. this command is also supported in qpi mode. in qpi mo de the instruction is shifted in on io0-io3, two clock cycles per byte. figure 10.44 page program (pp 02h or 4pp 12h) qpi mode command sequence note: 1. a = msb of address = a23 for pp 02h, or a31 for 4pp 12h. cs# sck si so phase 7 6 5 4 3 2 1 0 a 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address input data 1 input data 2 cs# sclk io0 io1 io2 io3 phase 4 0 a-3 4 0 4 0 4 0 4 0 4 0 5 1 a-2 5 1 5 1 5 1 5 1 5 1 6 2 a-1 6 2 6 2 6 2 6 2 6 2 7 3 a 7 3 7 3 7 3 7 3 7 3 instruct. address input d1 input d2 input d3 input d4
november 6, 2013 s25fs-s_00_04 s25fs-s family 115 data sheet (preliminary) 10.6 erase flash array commands 10.6.1 parameter 4-kb sector erase (p4e 20h or 4p4e 21h) the main flash array address map may be configured to overlay 4-kb parameter sectors over the lowest address portion of the lowest address uniform sector (b ottom parameter sectors) or over the highest address portion of the highest address uniform sector (top param eter sectors). the main flash array address map may also be configured to have only uniform size sectors. the parameter sector confi guration is controlled by the configuration bit cr3v[3]. the p4e and 4p4e commands are ignored when the device is configured for uniform sectors only (cr3v[3]=1). the parameter 4-kb sector erase comm ands set all the bits of a 4-kb param eter sector to 1 (all bytes are ffh). before the p4e or 4p4e command can be acce pted by the device, a writ e enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the instruction ? 20h [cr2v[7]=0] is followed by a 3-byte address (a23-a0), or ? 20h [cr2v[7]=1] is followed by a 4-byte address (a31-a0), or ? 21h is followed by a 4-byte address (a31-a0) cs# must be driven into the logic high state after the twenty-fourth or thirty-sec ond bit of the address has been latched in on si. this will in itiate the beginning of internal erase cycle, which involves the pre- programming and erase of the chosen sect or of the flash memory array. if cs # is not driven high after the last bit of address, the sector er ase operation will not be executed. as soon as cs# is driven high, the internal erase cycl e will be initiated. with th e internal erase cycle in progress, the user can read the value of the write-in progress (wip) bit to determine when the operation has been completed. the wip bit will indicate a 1. when the erase cycle is in progress and a 0 when the erase cycle has been completed. a p4e or 4p4e command applied to a sector that has been write protected through the block protection bits or asp, will not be executed and will set the e_err status . a p4e command applied to a sector that is larger than 4 kbytes will not be executed and will not set the e_err status. figure 10.45 parameter sector erase (p4e 20h or 4p4e 21h) command sequence note: 1. a = msb of address = a23 for p4e 20h with cr2v[7]=0, or a31 for p4e 20h with cr2v[7]=1 or 4p4e 21h. this command is also supported in qpi mode. in qpi mo de the instruction is shifted in on io0-io3, two clock cycles per byte. cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 instruction address
116 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) figure 10.46 parameter sector erase (p4e 20h or 4p4e 21h) qpi mode command sequence note: 1. a = msb of address = a23 for p4e 20h with cr2v[7]=0, or a31 for p4e 20h with cr2v[7]=1 or 4p4e 21h. 10.6.2 sector erase (s e d8h or 4se dch) the sector erase (se) command sets all bits in the ad dressed sector to 1 (all bytes are ffh). before the sector erase (se) command can be accepted by th e device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the instruction ? d8h [cr2v[7]=0] is followed by a 3-byte address (a23-a0), or ? d8h [cr2v[7]=1] is followed by a 4-byte address (a31-a0), or ? dch is followed by a 4-byte address (a31-a0) cs# must be driven into the logic high state after t he twenty-fourth or thirty-s econd bit of address has been latched in on si. this will initiate the erase cycle, which involves the pre-programming and erase of the chosen sector. if cs# is not driven high after the last bit of address, the sector erase operation will not be executed. as soon as cs# is driven into the logic high state, t he internal erase cycle will be in itiated. with the internal erase cycle in progress, the user can read the value of the write-in progress (w ip) bit to check if the operation has been completed. the wip bit will indicate a 1 when the erase cycle is in progress and a 0 when the erase cycle has been completed. a sector erase (se) command applied to a sector that has been write protected th rough the block protection bits or asp, will not be executed and will set the e_err status. a device configuration option (cr3v[1]) determines whether the se command erases 64 kbytes or 256 kbytes. the option to use this command to always erase 256 kbytes provides for software compatibility with higher density and future s25fs family devices. a device configuration option (cr3v[3]) determines wh ether 4-kb parameter sectors are in use. when cr3v[3] = 0, 4-kb parameter sectors overlay a portion of the highest or lowest address 32 kb of the device address space. if a sector erase command is applied to a 64- kb sector that is overlaid by 4-kb sectors, the overlaid 4-kb sectors are not affected by the erase. only the visible (n on-overlaid) portion of the 64-kb sector appears erased. similarly if a sector erase command is a pplied to a 256-kb range that is overlaid by 4-kb sectors, the overlaid 4-kb sector s are not affected by the erase. when cr3v[3] = 1, there are no 4-kb parameter sectors in the device address space and the sector erase command always operates on fully visible 64-kb or 256-kb sectors. asp has a ppb and a dyb protection bit for each physical sector, including any 4-kb sectors. if a sector erase command is applied to a 256-kb range that includ es a 64-kb protected physical sector, the erase will not be executed on the 256-kb range and will set the e_err status. cs# sclk io0 io1 io2 io3 phase 4 0 a-3 4 0 5 1 a-2 5 1 6 2 a-1 6 2 7 3 a 7 3 instructtion address
november 6, 2013 s25fs-s_00_04 s25fs-s family 117 data sheet (preliminary) figure 10.47 sector erase (se d8h or 4se dch) command sequence note: 1. a = msb of address = a23 for se d8h with cr2v[7]=0, or a31 for se d8h with cr2v[7]=1 or 4p4e dch. this command is also supported in qpi mode. in qpi mo de the instruction is shifted in on io0-io3, two clock cycles per byte. figure 10.48 sector erase (se d8h or 4se dch) qpi mode command sequence note: 1. a = msb of address = a23 for p4e 20h with cr2v[7]=0, or a31 for p4e 20h with cr2v[7]=1 or 4p4e 21h. cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 instruction address cs# sclk io0 io1 io2 io3 phase 4 0 a-3 4 0 5 1 a-2 5 1 6 2 a-1 6 2 7 3 a 7 3 instructtion address
118 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 10.6.3 bulk erase (be 60h or c7h) the bulk erase (be) command sets all bits to 1 (all bytes are ffh) inside the entire flash memory array. before the be command can be accepted by the devic e, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. cs# must be driven into the logic high state after the ei ghth bit of the instruction byte has been latched in on si. this will initiate the erase cycle, which involves the pre-programming and erase of the entire flash memory array. if cs# is not driven high after the last bit of instruction, the be operation will not be executed. as soon as cs# is driven into the logic high state, the erase cycle will be initiat ed. with the erase cycle in progress, the user can read the value of the write-in progress (wip) bit to determine when the operation has been completed. the wip bit will indicate a 1 when the erase cycle is in progress and a 0 when the erase cycle has been completed. a be command can be executed only when the block protec tion (bp2, bp1, bp0) bits are set to 0s. if the bp bits are not 0, the be command is not executed and e_err is not set. the be command will skip any sectors protected by the dyb or ppb and the e_err status will not be set. figure 10.49 bulk erase command sequence this command is also supported in qpi mode. in qpi mo de the instruction is shifted in on io0-io3, two clock cycles per byte. figure 10.50 bulk erase command sequence qpi mode cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction
november 6, 2013 s25fs-s_00_04 s25fs-s family 119 data sheet (preliminary) 10.6.4 evaluate erase status (ees d0h) the evaluate erase status (ees) command verifies that the last erase operation on the addressed sector was completed successfully. if the sele cted sector was successfu lly erased the erase st atus bit (sr2v[2]) is set to 1. if the selected sector was not completely erased sr2v[2] is 0. the ees command can be used to detect erase operations failed due to loss of power, reset, or failure during the erase operation. the ees instruction is followed by a 3- or 4-byte address, depending on the add ress length configuration (cr2v[7]). the ees command requires t ees to complete and update the er ase status in sr2v. the wip bit (sr1v[0]) may be read usi ng the rdsr1 (05h) command , to determine when the ees command is finished. then the rdsr2 (07h) or the rdar (65h) command can be used to read sr2v[2]. if a sector is found not erased with sr2v[2]=0, the sector must be erased again to ensure reliable storage of data in the sector. the write enable command (to set the wel bit) is not required befor e the ees command. however, the wel bit is set by the device itself and cleared at the end of the operation, as visible in sr1v[1] when reading status. figure 10.51 ees command sequence note: 1. a = msb of address = a23 for cr2v[7]=0, or a31 for cr2v[7]=1. this command is also supported in qpi mode. in qpi mo de the instruction is shifted in on io0-io3, two clock cycles per byte. figure 10.52 ees qpi mode command sequence note: 1. a = msb of address = a23 for cr2v[7]=0, or a31 for cr2v[7]=1. cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 instruction address cs# sclk io0 io1 io2 io3 phase 4 0 a-3 4 0 5 1 a-2 5 1 6 2 a-1 6 2 7 3 a 7 3 instructtion address
120 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 10.6.5 program or erase su spend (pes 85h, 75h, b0h) there are three instruction codes for program or erase suspend (pes) to enable legacy and alternate source software compatibility. the pes command allows the system to interrupt a pr ogramming or erase operation and then read from any other non-erase-suspended sector or non-program-suspended-page. program or erase suspend is valid only during a programming or sector erase operation. a bulk erase operation cannot be suspended. the write-in-progress (wip) bit in status register 1 (sr1v[0]) must be checked to know when the programming or erase operation has stopped. the program suspend status bit in the status register 2 (sr2[0]) can be used to determine if a programming operation has been suspended or was completed at the time wip changes to 0. the erase suspend status bit in the status register 2 (sr2[1]) can be used to determine if an erase operation has been suspended or was completed at the time wip changes to 0. the time required for the suspend operation to complete is t sl , see table 11.2, program or erase suspend ac parameters on page 134 . an erase can be suspended to allow a program operation or a read operation. during an erase suspend, the dyb array may be read to examine sector protection and written to remove or restore protection on a sector to be programmed. a program operation may be suspended to allow a read operation. a new erase operation is not allowed with an alre ady suspended erase or program operation. an erase command is ignored in this situation. table 10.5 commands allowed during program or erase suspend (sheet 1 of 2) instruction name instruction code (hex) allowed during erase suspend allowed during program suspend comment pp 02 x required for array program during erase suspend. only allowed if there is no other program suspended program operation (sr2v[0]=0). a program command will be ignored while there is a suspended program. if a program command is sent for a location within an erase suspended sector the program operation will fail with the p_err bit set. read 03 x x all array reads allowed in suspend. rdsr1 05 x x needed to read wip to determine end of suspend process. rdar 65 x x alternate way to read wip to determine end of suspend process. wren 06 x required for program command within erase suspend. rdsr2 07 x x needed to read suspend status to determine whether the operation is suspended or complete. 4pp 12 x required for array program during erase suspend. only allowed if there is no other program suspended program operation (sr2v[0]=0). a program command will be ignored while there is a suspended program. if a program command is sent for a location within an erase suspended sector the program operation will fail with the p_err bit set. 4read 13 x x all array reads allowed in suspend. clsr 30 x clear status may be used if a program operation fails during erase suspend. note the instruction is only valid if enabled for clear status by cr4nv[2=1]. clsr 82 x clear status may be used if a program operation fails during erase suspend. epr 30 x x required to resume from erase or program suspend. note the command must be enabled for use as a resume command by cr4nv[2]=0. epr 7a x x required to resume from erase or program suspend. epr 8a x x required to resume from erase or program suspend. rsten 66 x x reset allowed anytime. rst 99 x x reset allowed anytime. fast_read 0b x x all array reads allowed in suspend. 4fast_read 0c x x all array reads allowed in suspend. epr 7a x required to resume from erase suspend. epr 8a x required to resume from erase suspend. dior bb x x all array reads allowed in suspend.
november 6, 2013 s25fs-s_00_04 s25fs-s family 121 data sheet (preliminary) reading at any address within an erase-sus pended sector or program-suspended page produces undetermined data. the wrr, wrar, or ppb erase commands are not al lowed during erase or program suspend, it is therefore not possib le to alter the block protection or ppb bits du ring erase suspend. if there are sectors that may need programming during erase suspend, these sector s should be protected only by dyb bits that can be turned off during erase suspend. after an erase-suspended program operation is complete , the device returns to the erase-suspend mode. the system can determine the status of the program operat ion by reading the wip bit in the status register, just as in the standard program operation. figure 10.53 program or erase suspend command sequence figure 10.54 program or erase suspend command sequence 4dior bc x x all array reads allowed in suspend. dybrd fa x it may be necessary to remove and restore dynamic protection during erase suspend to allow programming during erase suspend. dybwr fb x it may be necessary to remove and restore dynamic protection during erase suspend to allow programming during erase suspend. ppbrd fc x allowed for checking persistent protection before attempting a program command during erase suspend. 4dybrd e0 x it may be necessary to remove and restore dynamic protection during erase suspend to allow programming during erase suspend. 4dybwr e1 x it may be necessary to remove and restore dynamic protection during erase suspend to allow programming during erase suspend. 4ppbrd e2 x allowed for checking persistent protection before attempting a program command during erase suspend. qior eb x x all array reads allowed in suspend. 4qior ec x x all array reads allowed in suspend. ddrqior ed x x all array reads allowed in suspend. 4ddrqior ee x x all array reads allowed in suspend. reset f0 x x reset allowed anytime. mbr ff x x may need to reset a read operation during suspend. table 10.5 commands allowed during program or erase suspend (sheet 2 of 2) instruction name instruction code (hex) allowed during erase suspend allowed during program suspend comment cs# sck si so phase phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 suspend instruction read status instruction status instr. during suspend repeat status read until suspended tsl cs# sck si so phase 7 6 5 4 3 2 1 0 instruction
122 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) this command is also supported in qpi mode. in qpi mo de the instruction is shifted in on io0-io3, two clock cycles per byte. figure 10.55 program or erase suspend command sequence qpi mode 10.6.6 erase or program resu me (epr 7ah, 8ah, 30h) there are three instruction codes for erase or progra m resume (epr) to enable legacy and alternate source software compatibility. after program or read operations are completed duri ng a program or erase suspend the erase or program resume command is sent to continue the suspended operation. after an erase or program resume command is issued, th e wip bit in the status register 1 will be set to a 1 and the programming operation will resume if one is suspended. if no program operation is suspended the suspended erase operation will resume. if there is no suspended program or erase operation the resume command is ignored. program or erase operations may be interrupted as often as necessary e.g. a program suspend command could immediately follow a program resume command bu t, in order for a program or erase operation to progress to completion there must be some periods of time between resume and the next suspend command greater than or equal to t rs . see table 11.2, program or erase suspend ac parameters on page 134 . an erase or program resume command must be written to resume a suspended operation. figure 10.56 erase or program resume command sequence figure 10.57 erase or program resume command sequence qpi mode cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction
november 6, 2013 s25fs-s_00_04 s25fs-s family 123 data sheet (preliminary) 10.7 one-time program array commands 10.7.1 otp program (otpp 42h) the otp program command programs data in the one-ti me program region, which is in a different address space from the main array data. the otp region is 1024 bytes so, the address bits from a31 to a10 must be 0 for this command. refer to otp address space on page 58 for details on the otp region. before the otp program command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, which sets the wr ite enable latch (wel) in the status register to enable any write operations. the wip bit in sr1v ma y be checked to determine when the operation is completed. the p_err bit in sr1v may be checked to determine if any error occurred during the operation. to program the otp array in bit granularity, the rest of the bits within a data byte can be set to 1. each region in the otp memory space can be programm ed one or more times, provided that the region is not locked. attempting to program 0s in a region that is locked will fail with the p_err bit in sr1v set to 1. programming ones, even in a protected area does not cause an error and does not set p_err. subsequent otp programming can be performed only on th e un-programmed bits (that is, 1 data). the protocol of the otp program command is the same as the page program command. see page program (pp 02h or 4pp 12h) on page 114 for the command sequence. 10.7.2 otp read (otpr 4bh) the otp read command reads data from the otp region. the otp region is 1024 bytes so, the address bits from a31 to a10 must be zero for this command. refer to otp address space on page 58 for details on the otp region. the protocol of the otp read command is si milar to the fast read command except that it will not wrap to the starting address af ter the otp address is at its maximu m; instead, the data beyond the maximum otp address will be undefined. the otp read command read latency is set by the latency value in cr2v[3:0]. see fast read (fast_read 0bh or 4fast_read 0ch) on page 106 for the command sequence. 10.8 advanced sector protection commands 10.8.1 asp r ead (asprd 2bh) the asp read instruction 2bh is shifted into si by the rising edge of the sck signal. then the 16-bit asp register contents are shifted out on the serial output so, le ast significant byte first. each bit is shifted out at the sck frequency by the falling edge of the sck signal. it is possible to read the asp register continuously by providing multiples of 16 clock cycles. the maximum operating clock frequency for the asp read (asprd) command is 133 mhz. figure 10.58 asprd command cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction output aspr low byte output aspr high byte
124 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 10.8.2 asp program (aspp 2fh) before the asp program (aspp) command can be a ccepted by the device, a write enable (wren) command must be issued. after the write enable (w ren) command has been decoded, the device will set the write enable latch (wel) in the status register to enable any write operations. the aspp command is entered by driving cs# to the logic low state, followed by the instruction and two data bytes on si, least significant byte first. the asp register is two data bytes in length. the aspp command affects the p_err and wip bits of the status and co nfiguration registers in the same manner as any other programming operation. cs# input must be driven to the logic high state after th e sixteenth bit of data has been latched in. if not, the aspp command is not executed. as soon as cs# is dr iven to the logic high st ate, the self-timed aspp operation is initiated. while the aspp operation is in progress, the status register may be read to check the value of the write-in progress (wip ) bit. the write-in pr ogress (wip) bit is a 1 during the self-timed aspp operation, and is a 0 when it is completed. when t he aspp operation is completed, the write enable latch (wel) is set to a 0. figure 10.59 aspp command cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input aspr low byte input aspr high byte
november 6, 2013 s25fs-s_00_04 s25fs-s family 125 data sheet (preliminary) 10.8.3 dyb read (dybrd fah or 4dybrd e0h) the instruction is latched into si by the rising edge of the sck signal. the instruction is followed by the 24 or 32-bit address, depending on the address length configuration cr2v[7], selecting location zero within the desired sector. note, the high order address bits not us ed by a particular density device must be zero. then the 8-bit dyb access register contents are shifted out on the serial output so. each bit is shifted out at the sck frequency by the falling edge of the sck signal. it is possible to read the same dyb access register continuously by providing multiples of eight clock cycle s. the address of the dyb register does not increment so this is not a means to read the entire dyb array. each location must be read with a separate dyb read command. the maximum operating clock frequency for read command is 133 mhz. figure 10.60 dybrd command sequence notes: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7]=1 with command fah. 2. a = msb of address = 31 with command e0h. this command is also supported in qpi mode. in qpi mode the instruction and address is shifted in on io0- io3 and returning data is shifted out on io0-io3. figure 10.61 dybrd qpi mode command sequence notes: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7]=1 with command fah. 2. a = msb of address = 31 with command e0h. cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address register repeat register cs# sclk io0 io1 io2 io3 phase 4 0 a-3 4 0 4 0 5 1 a-2 5 1 5 1 6 2 a-1 6 2 6 2 7 3 a 7 3 7 3 instruction address output dybar
126 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 10.8.4 dyb write (dybwr fbh or 4dybwr e1h) before the dyb write (dybwr) command can be accept ed by the device, a write enable (wren) command must be issued. after the write enable (wren) comm and has been decoded, the device will set the write enable latch (wel) in the status regi ster to enable any write operations. the dybwr command is entered by driving cs# to the logi c low state, followed by the instruction, followed by the 24- or 32-bit address, depend ing on the address length configuratio n cr2v[7], selecting location zero within the desired sector (not e, the high order address bits not used by a particular density device must be zero), then the data byte on si. the dyb access register is one data byte in length. the data value must be 00h to protect or ffh to unprotect the selected sector. the dybwr command affects the p_err and wip bits of the status and configur ation registers in the same manner as any other programming operation. cs# must be driven to the logic high state after the eighth bit of data has been latched in. as soon as cs# is driven to the logic high st ate, the self-timed dybwr operation is initiated. while the dybwr operation is in progress, the status register may be read to check the value of the write-in progress (wip) bit. the writ e-in progress (wip) bit is a 1 during the self-timed dybwr operation, and is a 0 when it is completed. when the dybwr operation is completed, the write enable latch (wel) is set to a 0. figure 10.62 dybwr command sequence notes: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7]=1 with command fbh. 2. a = msb of address = 31 with command e1h. this command is also supported in qpi mode. in qpi mo de the instruction is shifted in on io0-io3, two clock cycles per byte. figure 10.63 dybwr qpi mode command sequence note 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7]=1 with command fbh. 2. a = msb of address = 31 with command e1h cs# sck si so phase 7 6 5 4 3 2 1 0 a 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address input data cs# sclk io0 io1 io2 io3 phase 4 0 a-3 4 0 4 0 5 1 a-2 5 1 5 1 6 2 a-1 6 2 6 2 7 3 a 7 3 7 3 instruction address input dybar
november 6, 2013 s25fs-s_00_04 s25fs-s family 127 data sheet (preliminary) 10.8.5 ppb read (ppbrd fch or 4ppbrd e2h) the instruction e2h is shifted into si by the rising e dges of the sck signal, followed by the 24- or 32-bit address, depending on the address length configuration cr2v[7], selecting location zero within the desired sector (note, the high order address bits not used by a particular density device must be zero). then the 8-bit ppb access register conten ts are shifted out on so. it is possible to read the same ppb access register continuously by providing multiples of eight clock cycles. the address of the ppb r egister does not increment so this is not a means to read the entire ppb array. each location must be read with a separate ppb read command. the maximum operating clock frequency for the ppb read command is 133 mhz. figure 10.64 ppbrd command sequence notes: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7]=1 with command fch. 2. a = msb of address = 31 with command e2h. 10.8.6 ppb program (ppb p fdh or 4ppbp e3h) before the ppb program (ppbp) command can be a ccepted by the device, a write enable (wren) command must be issued. after the write enable (w ren) command has been decoded, the device will set the write enable latch (wel) in the status register to enable any write operations. the ppbp command is entered by driving cs# to the logic low state, followed by the instruction, followed by the 24- or 32-bit address, depending on the address leng th configuration cr2v[7], selecting location zero within the desired sector (not e, the high order address bits not used by a particular density device must be zero). the ppbp command affects the p_err and wip bits of the status and co nfiguration registers in the same manner as any other programming operation. cs# must be driven to the logic high state after the last bit of addre ss has been latched in . if not, the ppbp command is not executed. as soon as cs# is driven to the logic high state, the self-timed ppbp operation is initiated. while the ppbp operation is in progress, the status register may be read to check the value of the write-in progress (wip) bit. the wip bit is a 1 during the self-timed ppbp operation, and is a 0 when it is completed. when the ppbp operation is completed, the write enable latch (wel) is set to a 0. figure 10.65 ppbp command sequence notes: 1. a = msb of address = 23 for address length (cr2v[7] = 0, or 31 for cr2v[7]=1 with command fdh. 2. a = msb of address = 31 with command e3h. cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address register repeat register cs# sck si so phase 7 6 5 4 3 2 1 0 a 1 0 instruction address
128 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 10.8.7 ppb erase (ppbe e4h) the ppb erase (ppbe) command sets al l ppb bits to 1. before the ppb erase command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the instruction e4h is shifted into si by the rising edges of the sck signal. cs# must be driven into the logic high state after the ei ghth bit of the instruction byte has been latched in on si. this will initiate the beginning of internal erase cycle, which involves the pre-prog ramming and erase of the entire ppb memory array. without cs# being driven to the logic high state afte r the eighth bit of the instruction, the ppb erase o peration will not be executed. with the internal erase cycle in progress, the user can read the value of the writ e-in progress (wip) bit to check if the operation has been completed. the wip bit will indicate a 1 when the erase cycle is in progress and a 0 when the erase cycle has been completed. eras e suspend is not allowed during ppb erase. figure 10.66 ppb erase command sequence 10.8.8 ppb lock bit read (plbrd a7h) the ppb lock bit read (plbrd) command allows the ppb lock register contents to be read out of so. it is possible to read the ppb lock register continuously by providing multiple s of eight clock cycles. the ppb lock register contents may only be read when the device is in standby state with no othe r operation in progress. it is recommended to check the write-in progress (wip) bit of the status register before issuing a new command to the device. figure 10.67 ppb lock register read command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction register read repeat register read
november 6, 2013 s25fs-s_00_04 s25fs-s family 129 data sheet (preliminary) 10.8.9 ppb lock bit write (plbwr a6h) the ppb lock bit write (plbwr) command clears the ppb lock regist er to zero. before the plbwr command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device, which sets the write enable latch (wel) in the status register to enable any write operations. the plbwr command is entered by driving cs# to the logic low state, followed by the instruction. cs# must be driven to the logic high state after the ei ghth bit of instruction has been latched in. if not, the plbwr command is not executed. as soon as cs# is dr iven to the logic high st ate, the self-timed plbwr operation is initiated. while the plbwr operation is in progress, the status regist er may still be read to check the value of the write-in progress (wip) bit. the write-in progress (wip) bit is a 1 during the self-timed plbwr operation, and is a 0 when it is completed. when the plbwr operation is completed, the write enable latch (wel) is set to a 0. the maximu m clock frequency for the plbwr command is 133 mhz. figure 10.68 ppb lock bit write command sequence 10.8.10 password read (passrd e7h) the correct password value may be read only after it is programmed and before the password mode has been selected by programming t he password protection mode bit to 0 in the asp register (asp[2]). after the password protection mode is selected the passwor d is no longer readable, the passrd command will output undefined data. the passrd command is shifted into si . then the 64-bit password is shifted out on the serial output so, least significant byte first, most signific ant bit of each byte first. each bit is shifted out at the sck frequency by the falling edge of the sck signal. it is possible to re ad the password continuously by providing multiples of 64 clock cycles. the maximum operating clock fr equency for the passrd command is 133 mhz. figure 10.69 password read command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction data 1 data n
130 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 10.8.11 password program (passp e8h) before the password program (passp) command can be accepted by the device, a write enable (wren) command must be issued and decoded by the device. after the write enable (wren) command has been decoded, the device sets the write enabl e latch (wel) to enable the passp operation. the password can only be programmed before the pa ssword mode is selected by programming the password protection mode bit to 0 in the asp register (asp[2]). afte r the password protection mode is selected the passp co mmand is ignored. the passp command is entered by driving cs# to the l ogic low state, followed by the instruction and the password data bytes on si, least signif icant byte first, most significant bit of each byte first. the password is sixty-four (64) bits in length. cs# must be driven to the logic high state after the sixty-fourth (64 th ) bit of data has been latched. if not, the passp command is not executed. as soon as cs# is driven to the logic high st ate, the self-timed passp operation is initiated. while the passp operation is in progress, the status regi ster may be read to check the value of the write-in progress (wip ) bit. the write-in pr ogress (wip) bit is a 1 during the self-timed passp cycle, and is a 0 when it is comple ted. the passp command can report a program error in the p_err bit of the status register. when the passp op eration is completed, the write enable latch (wel) is set to a 0. the maximum clock frequency for the passp command is 133 mhz. figure 10.70 password program command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input password low byte input password high byte
november 6, 2013 s25fs-s_00_04 s25fs-s family 131 data sheet (preliminary) 10.8.12 password unlock (passu e9h) the passu command is entered by dr iving cs# to the logic low state, followed by the instruction and the password data bytes on si, least signif icant byte first, most significant bit of each byte first. the password is sixty-four (64) bits in length. cs# must be driven to the logic high state after the sixty-fourth (64 th ) bit of data has been latched. if not, the passu command is not executed. as soon as cs# is dr iven to the logic high state, the self-timed passu operation is initiated. while the passu operation is in progress, the status register may be read to check the value of the write-in progress (wip ) bit. the write-in pr ogress (wip) bit is a 1 during the self-timed passu cycle, and is a 0 when it is completed. if the passu command supplied password does not ma tch the hidden password in the password register, an error is reported by setting the p_err bit to 1. the wip bit of the status register also remains set to 1. it is necessary to use the clsr comman d to clear the status register, t he reset command to software reset the device, or drive the reset# input low to initiate a hardware reset, in order to return the p_err and wip bits to 0. this returns the device to standby state, ready for new commands su ch as a retry of the passu command. if the password does match, the ppb lock bit is set to 1. the ma ximum clock frequency for the passu command is 133 mhz. figure 10.71 password unlock command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input password low byte input password high byte
132 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 10.9 reset commands software controlled reset commands re store the device to its initial power-up state, by reloading volatile registers from non-volatile default va lues. however, the volatile freeze bit in the configuration register cr1v[0] and the volatile ppb lock bit in the ppb lock register are not changed by a software reset. the software reset cannot be used to circumvent the freeze or ppb lock bit protection mechanisms for the other security configuration bits. the freeze bit and the ppb lock bit will remain set at thei r last value prior to the software reset. to clear the freeze bit and set the ppb lock bit to its protection mode selected power-on state, a full power-on-reset sequence or hardware reset must be done. the non-volatile bits in the configuration regist er (cr1nv), tbprot_o, tbparm, and bpnv_o, retain their previous state after a software reset. the block protection bits bp2, bp1, and bp0, in the status register (sr1v) will only be reset to their default value if freeze = 0. a reset command (rst or reset) is executed when cs# is brought high at the end of the instruction and requires t rph time to execute. in the case of a previous power-up reset (por) failure to complete, a reset command triggers a full power- up sequence requiring t pu to complete. figure 10.72 software reset command sequence this command is also supported in qpi mode. in qpi mo de the instruction is shifted in on io0-io3, two clock cycles per byte. figure 10.73 software reset command sequence qpi mode 10.9.1 software reset enable (rsten 66h) the reset enable (rsten) command is required immediately before a reset command (rst) such that a software reset is a sequence of the two commands. any command other than rst following the rsten command, will clear the reset enable condition and prevent a later rst command from being recognized. 10.9.2 software reset (rst 99h) the reset (rst) command immediately following a rsten command, initiates the software reset process. cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction
november 6, 2013 s25fs-s_00_04 s25fs-s family 133 data sheet (preliminary) 10.9.3 legacy software reset (reset f0h) the legacy software reset (reset) is a single command th at initiates the software reset process. this command is disabled by default but can be enabled by programming cr3v[0]=1, for software compatibility with spansion legacy fl-s devices. 10.9.4 mode bit reset (mbr ffh) the mode bit reset (mbr) command is used to return the device from continuous high performance read mode back to normal standby awaiting any new command. because some device packages lack a hardware reset# input and a device that is in a continuou s high performance read mode may not recognize any normal spi command, a system hardwa re reset or software reset command may not be recognized by the device. it is recommended to use the mbr command after a system reset when the reset# signal is not available or, before sending a software reset, to ensure the device is released from continuous high performance read mode. the mbr command sends 1s on si or io0 for 8 sck cycles. io1 to io3 ar e ?don?t care? during these cycles. figure 10.74 mode bit reset command sequence this command is also supported in qpi mode. in qpi mo de the instruction is shifted in on io0-io3, two clock cycles per byte. figure 10.75 mode bit reset command sequence qpi mode cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sclk io0 io1 io2 io3 phase 4 0 5 1 6 2 7 3 instruction
134 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 11. embedded algorithm performance tables the joint electron device engineering council (jed ec) standard jesd22-a117 defines the procedural requirements for performing valid endur ance and retention tests based on a qualification specification. this methodology is intended to determine the ability of a flash device to sustain repeated data changes without failure (program/erase endurance) and to retain data for the expected life (data retention). endurance and retention qualification specificati ons are specified in jesd47 or may be developed using knowledge-based methods as in jesd94. notes: 1. not 100% tested. 2. typical program and erase times assume the following conditions: 25c, v dd = 1.8v; random data pattern. 3. the programming time for any otp programming command is the same as t pp . this includes otpp 42h, pnvdlr 43h, aspp 2fh, and passp e8h. 4. the programming time for the ppbp e3h command is the same as t pp . the erase time for ppbe e4h command is the same as t se . 5. data retention of 20 years is based on 1k erase cycles or less. table 11.1 program and erase performance symbol parameter min typ (2) max unit t w non-volatile register write time 145 750 ms t pp page programming (512 bytes) page programming (256 bytes) 475 360 1080 1080 s t se sector erase time (64-kb or 4- kb physical sectors) 145 725 ms sector erase time (256-kb logical sectors = 4x64k physical sectors) 580 2900 ms t be (1) bulk erase time (s25fs128s) 36 180 sec t be (1) bulk erase time (s25fs256s) 72 360 sec t ees evaluate erase status time (64-kb or 4-kb physical sectors) 20 25 s evaluate erase status time (256-kb physical or logical sectors) 80 100 erase per sector 100,000 cycles table 11.2 program or erase suspend ac parameters parameter typical max unit comments suspend latency (t sl ) 40 s the time from suspend command until the wip bit is 0. resume to next program suspend (t rs ) 100 s minimum is the time needed to issue the next suspend command but typical periods are needed for program or erase to progress to completion.
november 6, 2013 s25fs-s_00_04 s25fs-s family 135 data sheet (preliminary) 12. software interface reference 12.1 command summary by instruction table 12.1 s25fs-s family command set (sorted by instruction) command name command description instruction value (hex) maximum frequency (mhz) address length (bytes) qpi wrr write register (status 1, configuration 1) 01 133 0 yes pp page program 02 133 3 or 4 yes read read 03 50 3 or 4 no wrdi write disable 04 133 0 yes rdsr1 read status register 1 05 133 0 yes wren write enable 06 133 0 yes rdsr2 read status register 2 07 133 0 no 4pp page program 12 133 4 yes 4read read 13 50 4 no p4e parameter 4-kb sector erase 20 133 3 or 4 yes 4p4e parameter 4-kb sector erase 21 133 4 yes clsr clear status register 1 - erase/prog. fail reset this command may be disabled and the instruction value instead used for a program / erase resume command - see configuration register 3 on page 69 30 133 0 yes epr erase / program resume (alternate instruction) this command may be disabled and the instruction value instead used for a clear status command - see configuration register 3 on page 69 30 133 0 yes rdcr read configuration register 1 35 133 0 no dlprd data learning pattern read 41 133 0 no otpp otp program 42 133 3 or 4 no pnvdlr program nv data learning register 43 133 0 no be bulk erase 60 133 0 yes rdar read any register 65 133 3 or 4 yes rsten software reset enable 66 133 0 yes wrar write any register 71 133 3 or 4 yes eps erase / program suspend 75 133 0 yes clsr clear status register 1 (alternate instruction) - erase/prog. fail reset 82 133 0 yes eps erase / program suspend (alternate instruction) 85 133 0 yes rst software reset 99 133 0 yes fast_read fast read 0b 133 3 or 4 no 4fast_read fast read 0c 133 4 no asprd asp read 2b 133 0 no aspp asp program 2f 133 0 no wvdlr write volatile data learning register 4a 133 0 no otpr otp read 4b 133 3 or 4 no rsfdp read jedec serial flash discoverable parameters 5a 50 3 yes epr erase / program resume 7a 133 0 yes epr erase / program resume (alternate instruction) 8a 133 0 yes rdid read id (jedec manufacturer id and jedec cfi) 9f 133 0 yes plbwr ppb lock bit write a6 133 0 no plbrd ppb lock bit read a7 133 0 no rdqid read quad id af 133 0 yes eps erase / program suspend (alternate instruction) b0 133 0 yes
136 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 12.2 registers the register maps are copied in this section as a quick reference. see registers on page 59 for the full description of the register contents. 4bam enter 4-byte address mode b7 133 0 no dior dual i/o read bb 66 3 or 4 no 4dior dual i/o read bc 66 4 no sbl set burst length c0 133 0 no be bulk erase (alternate instruction) c7 133 0 yes ees evaluate erase status d0 133 3 or 4 yes se erase 64 kb or 256 kb d8 133 3 or 4 yes 4se erase 64 kb or 256 kb dc 133 4 yes 4dybrd dyb read e0 133 4 yes 4dybwr dyb write e1 133 4 yes 4ppbrd ppb read e2 133 4 no 4ppbp ppb program e3 133 4 no ppbe ppb erase e4 133 0 no passrd password read e7 133 0 no passp password program e8 133 0 no passu password unlock e9 133 0 no qior quad i/o read eb 133 3 or 4 yes 4qior quad i/o read ec 133 4 yes ddrqior ddr quad i/o read ed 80 3 or 4 yes 4ddrqior ddr quad i/o read ee 80 4 yes reset legacy software reset f0 133 0 no dybrd dyb read fa 133 3 or 4 yes dybwr dyb write fb 133 3 or 4 yes ppbrd ppb read fc 133 3 or 4 no ppbp ppb program fd 133 3 or 4 no mbr mode bit reset ff 133 0 yes table 12.1 s25fs-s family command set (sorted by instruction) command name command description instruction value (hex) maximum frequency (mhz) address length (bytes) qpi table 12.2 status register 1 non-volatile (sr1nv) bits field name function type default state description 7 srwd_nv status register write disable default non-volatile 0 1 = locks state of srwd, bp, and configuration register 1 bits when wp# is low by not executing wrr or wrar commands that would affect sr1nv, sr1v, cr1nv, or cr1v. 0 = no protection, even when wp# is low. 6 p_err_d programming error default non-volatile read only 0 provides the default state for the programming error status. not user programmable. 5 e_err_d erase error default non-volatile read only 0 provides the default state for the erase error status. not user programmable. 4 bp_nv2 block protection non-volatile non-volatile 000b protects the selected range of sectors (block) from program or erase when the bp bits are configured as non-volatile (cr1nv[3]=0). programmed to 111b when bp bits are configured to volatile (cr1nv[3]=1).- after which these bits are no longer user programmable. 3 bp_nv1 2 bp_nv0 1 wel_d wel default non-volatile read only 0 provides the default state for the wel status. not user programmable. 0 wip_d wip default non-volatile read only 0 provides the default state for the wip status. not user programmable.
november 6, 2013 s25fs-s_00_04 s25fs-s family 137 data sheet (preliminary) table 12.3 status register 1 volatile (sr1v) bits field name function type default state description 7 srwd status register write disable volatile read only sr1nv volatile copy of sr1nv[7]. 6 p_err programming error occurred volatile read only 1 = error occurred. 0 = no error. 5 e_err erase error occurred volatile read only 1= error occurred. 0 = no error. 4 bp2 block protection volatile volatile protects selected range of sectors (block) from program or erase when the bp bits are configured as volatile (cr1nv[3]=1). volatile copy of sr1nv[4:2] when bp bits are configured as non-volatile. user writable when bp bits are configured as volatile. 3 bp1 2 bp0 1 wel write enable latch volatile 1 = device accepts write registers (wrr and wrar), program, or erase commands. 0 = device ignores write registers (wrr and wrar), program, or erase commands. this bit is not affected by wrr or wrar, only wren and wrdi commands affect this bit. 0 wip write-in- progress volatile read only 1= device busy, an embedded operation is in progress such as program or erase. 0 = ready device is in standby mode and can accept commands. this bit is not affected by wrr or wrar, it only provides wip status. table 12.4 status register 2 volatile (sr2v) bits field name function type default state description 7 rfu reserved 0 reserved for future use. 6 rfu reserved 0 reserved for future use. 5 rfu reserved 0 reserved for future use. 4 rfu reserved 0 reserved for future use. 3 rfu reserved 0 reserved for future use. 2 estat erase status volatile read only 0 1 = sector erase status command result = erase completed. 0 = sector erase status command result = erase not completed. 1 es erase suspend volatile read only 0 1 = in erase suspend mode. 0 = not in erase suspend mode. 0 ps program suspend volatile read only 0 1 = in program suspend mode. 0 = not in program suspend mode.
138 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) table 12.5 configuration register 1 non-volatile (cr1nv) bits field name function type default state description 7 rfu reserved for future use non-volatile 0 reserved. 6 rfu 0 5 tbprot_o configures start of block protection otp 0 1 = bp starts at bottom (low address). 0 = bp starts at top (high address). 4 rfu reserved for future use rfu 0 reserved. 3 bpnv_o configures bp2-0 in status register otp 0 1 = volatile. 0 = non-volatile. 2 tbparm_o configures parameter sectors location otp 0 1 = 4-kb physical sectors at top, (high address). 0 = 4-kb physical sectors at bottom (low address). rfu in uniform sector configuration. 1 quad_nv quad non-volatile non-volatile 0 provides the default state for the quad bit. 0 freeze_d freeze default non-volatile read only 0 provides the default state for the freeze bit. not user programmable. table 12.6 configuration register 1 volatile (cr1v) bits field name function type default state description 7 rfu reserved for future use volatile cr1nv reserved. 6 rfu 5 tbprot volatile copy of tbprot_o volatile read only not user writable. see cr1nv[5] tbprot_o. 4 rfu reserved for future use rfu reserved. 3 bpnv volatile copy of bpnv_o volatile read only not user writable. see cr1nv[3] bpnv_o. 2 tbparm volatile copy of tbparm_o volatile read only not user writable. see cr1nv[2] tbparm_o. 1 quad quad i/o mode volatile 1 = quad. 0 = dual or serial. 0 freeze lock-down block protection until next power cycle volatile lock current state of block protection control bits, and otp regions. 1 = block protection and otp locked. 0 = block protection and otp unlocked. table 12.7 configuration register 2 non-volatile (cr2nv) bits field name function type default state description 7 al_nv address length otp 0 1 = 4-byte address. 0 = 3-byte address. 6 qa_nv qpi 0 1 = enabled - qpi (4-4-4) protocol in use. 0 = disabled - legacy spi protocols in use, instruction is always serial on si. 5 io3r_nv io3 reset 0 1 = enabled - io3 is used as reset# input when cs# is high or quad mode is disabled cr1v[1]=1. 0 = disabled - io3 has no alternate function, hardware reset is disabled. 4 rfu reserved 0 reserved for future use. 3 rl_nv read latency 1 0 to 15 latency (dummy) cycles following read address or continuous mode bits. note that bit 3 has a default value of 1 and may be programmed one time to 0 but cannot be returned to 1. 2 0 1 0 0 0
november 6, 2013 s25fs-s_00_04 s25fs-s family 139 data sheet (preliminary) table 12.8 configuration register 2 volatile (cr2v) bits field name function type default state description 7 al address length volatile cr2nv 1 = 4 byte address. 0 = 3 byte address. 6 qa qpi 1 = enabled - qpi (4-4-4) protocol in use. 0 = disabled - legacy spi protocols in use, instruction is always serial on si. 5 io3r_s io3 reset 1 = enabled - io3 is used as reset# input when cs# is high or quad mode is disabled cr1v[1]=1. 0 = disabled - io3 has no alternate function, hardware reset is disabled. 4 rfu reserved reserved for future use. 3 rl read latency 0 to 15 latency (dummy) cycles following read address or continuous mode bits. 2 1 0 table 12.9 configuration register 3 non-volatile (cr3nv) bits field name function type default state description 7 rfu reserved otp 0 reserved for future use. 6 rfu reserved 0 reserved for future use. 5 bc_nv blank check 0 1 = blank check during erase enabled. 0 = blank check disabled. 4 02h_nv page buffer wrap 0 1 = wrap at 512 bytes. 0 = wrap at 256 bytes. 3 20h_nv 4-kb erase 0 1 = 4-kb erase disabled (uniform sector architecture). 0 = 4-kb erase enabled (hybrid sector architecture). 2 30h_nv clear status / resume select 0 1 = 30h is erase or program resume command. 0 = 30h is clear status command. 1 d8h_nv block erase size 0 1 = 256-kb erase. 0 = 64-kb erase. 0 f0h_nv legacy software reset enable 0 1 = f0h software reset is enabled. 0 = f0h software reset is disabled (ignored). table 12.10 configuration register 3 volatile (cr3v) bits field name function type default state description 7 rfu reserved volatile cr3nv reserved for future use. 6 rfu reserved reserved for future use. 5 bc_v blank check 1 = blank check during erase enabled. 0 = blank check disabled. 4 02h_v page buffer wrap 1 = wrap at 512 bytes. 0 = wrap at 256 bytes. 3 20h_v 4-kb erase volatile, read only 1 = 4-kb erase disabled (uniform sector architecture). 0 = 4-kb erase enabled (hybrid sector architecture). 2 30h_v clear status / resume select volatile 1 = 30h is erase or program resume command. 0 = 30h is clear status command. 1 d8h_v block erase size 1 = 256-kb erase. 0 = 64-kb erase. 0 f0h_v legacy software reset enable 1 = f0h software reset is enabled. 0 = f0h software reset is disabled (ignored).
140 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) table 12.11 configuration register 4 non-volatile (cr4nv) bits field name function type default state description 7 oi_o output impedance otp 0 see table 8.25, output impedance control on page 71 . 6 0 5 0 4 we_o wrap enable 1 0 = wrap enabled. 1 = wrap disabled. 3 rfu reserved 0 reserved for future use. 2 rfu reserved 0 reserved for future use. 1 wl_o wrap length 0 00 = 8-byte wrap. 01 = 16-byte wrap. 10 = 32-byte wrap. 11 = 64-byte wrap. 0 0 table 12.12 configuration register 4 volatile (cr4v) bits field name function type default state description 7 oi output impedance volatile cr4nv see table 8.25, output impedance control on page 71 . 6 5 4 we wrap enable 0 = wrap enabled. 1 = wrap disabled. 3 rfu reserved reserved for future use. 2 rfu reserved reserved for future use. 1 wl wrap length 00 = 8-byte wrap. 01 = 16-byte wrap. 10 = 32-byte wrap. 11 = 64-byte wrap. 0 table 12.13 asp register (aspr) bits field name function type default state description 15 to 9 rfu reserved otp 1 reserved for future use. 8 rfu reserved otp 1 reserved for future use. 7 rfu reserved otp 1 reserved for future use. 6 rfu reserved otp 1 reserved for future use. 5 rfu reserved otp 1 reserved for future use. 4 rfu reserved rfu 1 reserved for future use. 3 rfu reserved rfu 1 reserved for future use. 2 pwdmlb password protection mode lock bit otp 1 0 = password protection mode permanently enabled. 1 = password protection mode not permanently enabled. 1 pstmlb persistent protection mode lock bit otp 1 0 = persistent protection mode permanently enabled. 1 = persistent protection mode not permanently enabled. 0 rfu reserved rfu 1 reserved for future use.
november 6, 2013 s25fs-s_00_04 s25fs-s family 141 data sheet (preliminary) table 12.14 password register (pass) bits field name function type default state description 63 to 0 pwd hidden password otp ffffffff- ffffffffh non-volatile otp storage of 64-bit password. the password is no longer readable after the password protection mode is selected by programming asp register bit 2 to 0. table 12.15 ppb lock register (ppbl) bits field name function type default state description 7 to 1 rfu reserved volatile 00h reserved for future use 0 ppblock protect ppb array volatile read only aspr[2:1] = 1xb = persistent protection mode = 1 aspr[2:1] = 01b = password protection mode = 0 0 = ppb array protected. 1 = ppb array may be programmed or erased. table 12.16 ppb access register (ppbar) bits field name function type default state description 7 to 0 ppb read or program per sector ppb non-volatile ffh 00h = ppb for the sector addressed by the ppbrd or ppbp command is programmed to 0, protecting that sector from program or erase operations. ffh = ppb for the sector addressed by the ppbrd command is 1, not protecting that sector from program or erase operations. table 12.17 dyb access register (dybar) bits field name function type default state description 7 to 0 dyb read or write per sector dyb volatile ffh 00h = dyb for the sector addressed by the dybrd or dybwr command is cleared to 0, protecting that sector from program or erase operations. ffh = dyb for the sector addressed by the dybrd or dybwr command is set to 1, not protecting that sector from program or erase operations. table 12.18 non-volatile data learning register (nvdlr) bits field name function type default state description 7 to 0 nvdlp non-volatile data learning pattern otp 00h otp value that may be transferred to the host during ddr read command latency (dummy) cycles to provide a training pattern to help the host more accurately center the data capture point in the received data bits. table 12.19 volatile data learning register (vdlr) bits field name function type default state description 7 to 0 vdlp volatile data learning pattern volatile takes the value of nvdlr during por or reset volatile copy of the nvdlp used to enable and deliver the data learning pattern (dlp) to the outputs. the vdlp may be changed by the host during system operation.
142 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 12.3 serial flash discoverable pa rameters (sfdp) address map the sfdp address space has a header starting at address zero that identifies the sfdp data structure and provides a pointer to each parameter. one paramet er is mandated by the jedec jesd216 standard. spansion provides an additional parameter by pointing to the id-cfi address space i.e. the id-cfi address space is a sub-set of the sfdp a ddress space. the jedec parameter is located within the id-cfi address space and is thus both a cfi parameter and an sfdp parameter. in this way both sfdp and id-cfi information can be accessed by either the rsfdp or rdid commands. 12.3.1 field definitions table 12.20 sfdp overview map relative byte address offset sfdp dword address description 0000h 00h location zero within sfdp space - start of sfdp header. ,,, ... remainder of sfdp header followed by undefined space. 1000h 400h location zero within id-cfi space - start of id-cfi. ... ... id-cfi parameters. 1120h 448h start of sfdp jedec parameter which is also part of a cfi parameter. ... ... remainder of sfdp jedec parameter followed by either more cfi parameters or undefined space. table 12.21 sfdp header relative byte address offset sfdp dword address data description 00h 00h 53h this is the entry point for read sfdp (5ah) command i.e. location zero within sfdp space ascii ?s? 01h 46h ascii ?f? 02h 44h ascii ?d? 03h 50h ascii ?p? 04h 01h 00h sfdp minor revision 05h 01h sfdp major revision 06h 01h number of parameter headers (zero based, 01h = 2 parameters) 07h ffh unused 08h 02h 00h manufacturer id (jedec sfdp mandatory parameter) 09h 00h parameter minor revision 0ah 01h parameter major revision 0bh 09h parameter table length (in double words = dwords = 4 byte units) 0ch 03h 48h parameter table pointer byte 0 (dword = 4-byte aligned) jedec parameter byte offset = 1120h = 448h dword address 0dh 04h parameter table pointer byte 1 0eh 00h parameter table pointer byte 2 0fh ffh unused 10h 04h 01h manufacturer id (spansion) 11h 00h parameter minor revision 12h 01h parameter major revision 13h 51h parameter table length (in double words = dwords = 4-byte units) 14h 05h 00h parameter table pointer byte 0 (dword = 4-byte aligned) entry point for id-cfi parameter is byte offset = 1000h relative to sfdp location zero. 1000h bytes = 400h dwords 15h 04h parameter table pointer byte 1 16h 00h parameter table pointer byte 2 17h ffh unused
november 6, 2013 s25fs-s_00_04 s25fs-s family 143 data sheet (preliminary) 12.4 device id and common flash in terface (id-cfi) address map 12.4.1 field definitions table 12.22 manufacturer and device id byte address data description 00h 01h manufacturer id for spansion 01h 20h (128 mb) 02h (256 mb) device id most significant byte - memory interface type 02h 18h (128 mb) 19h (256 mb) device id least significant byte - density 03h 4dh id-cfi length - number bytes following. adding this value to the current location of 03h gives the address of the last valid location in the id-cfi legacy address map. the legacy cfi address map ends with the primary vendor-specific extended query. the original legacy length is maintained for backward software compatibility. however, the cfi query identification string also includes a pointer to the alternate vendor-specific extended query that contains additional information related to the fs-s family. 04h 00h (uniform 256-kb physical sectors) 01h (uniform 64-kb physical sectors) physical sector architecture the s25fs-s family may be configured with or without 4-kb parameter sectors in addition to the uniform sectors. 05h 81h (s25fs-s family) family id 06h xxh ascii characters for model refer to ordering information on page 151 for the model number definitions. 07h xxh 08h xxh reserved 09h xxh reserved 0ah xxh reserved 0bh xxh reserved 0ch xxh reserved 0dh xxh reserved 0eh xxh reserved 0fh xxh reserved table 12.23 cfi query identification string byte address data description 10h 11h 12h 51h 52h 59h query unique ascii string ?qry? 13h 14h 02h 00h primary oem command set fl-p backward compatible command set id 15h 16h 40h 00h address for primary extended table 17h 18h 53h 46h alternate oem command set ascii characters ?fs? for spi (f) interface, s technology 19h 1ah 51h 00h address for alternate oem extended table
144 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) table 12.24 cfi system interface string byte address data description 1bh 17h v dd min. (erase/program): 100 millivolts bcd 1ch 19h v dd max. (erase/program): 100 millivolts bcd 1dh 00h v pp min. voltage (00h = no v pp present) 1eh 00h v pp max. voltage (00h = no v pp present) 1fh 09h typical timeout per single byte program 2 n s 20h 09h typical timeout for min. size page program 2 n s (00h = not supported) 21h 08h (4 kb or 64 kb) 0ah (256 kb) typical timeout per individual sector erase 2 n ms 22h 0fh (128 mb) 10h (256 mb) typical timeout for full chip erase 2 n ms (00h = not supported) 23h 02h max. timeout for byte program 2 n times typical 24h 02h max. timeout for page program 2 n times typical 25h 03h max. timeout per individual sector erase 2 n times typical 26h 03h max. timeout for full chip erase 2 n times typical (00h = not supported)
november 6, 2013 s25fs-s_00_04 s25fs-s family 145 data sheet (preliminary) note: 1. fs-s devices are user configurable to have either a hybrid sector architecture (with eight 4-kb sectors and all remaining sec tors are uniform 64 kb or 256 kb) or a uniform sector architecture with a ll sectors uniform 64 kb or 256 kb. fs-s devices are also user configurable to have the 4-kb parameter sectors at the top of memory address space. the cfi geometry information of the above t able is relevant only to the initial delivery state. all devices are initially shipped from spansion with the hybrid sector architectur e with the 4-kb sectors located at the bottom of the array address map. however, the device configuration tbparm bit cr1nv[2] may be programed to invert the sector map to place the 4-kb sectors at the top of the array address map. the 20h_nv bit (cr3nv[3} may be programmed to remove the 4-kb sectors from the address map. the flash device driver software must examine the tbparm and 20h_nv bits to determine if the sector map was inverted or hybrid sectors removed at a later time. table 12.25 device geometry definition for bo ttom boot initial delivery state byte address data description 27h 18h (128 mb) 19h (256 mb) device size = 2 n bytes; 28h 02h flash device interface description; 0000h = x8 only 0001h = x16 only 0002h = x8/x16 capable 0003h = x32 only 0004h = single i/o spi, 3-byte address 0005h = multi i/o spi, 3-byte address 0102h = multi i/o spi, 3- or 4-byte address 29h 01h 2ah 08h max. number of bytes in multi-byte write = 2 n 0000 = not supported 0008h = 256b page 2bh 00h 2ch 03h number of erase block regions within device 1 = uniform device, >1 = boot device 2dh 07h erase block region 1 information (refer to jedec jep137) 8 sectors = 8-1 = 0007h 4-kb sectors = 256 bytes x 0010h 2eh 00h 2fh 10h 30h 00h 31h 00h erase block region 2 information (refer to jedec jep137) 128 mb and 256 mb: 1 sector = 1-1 = 0000h 32-kb sector = 256 bytes x 0080h 32h 00h 33h 80h 34h 00h (128 mb) 00h (256 mb) 35h feh erase block region 3 information 128 mb and 256 mb: 255 sectors = 255-1 = 00feh (128 mb) 511 sectors = 511-1 = 01feh (256 mb) 64-kb sectors = 0100h x 256 bytes 36h 00h (128 mb) 01h (256 mb) 37h 00h 38h 01h (128 mb) 01h (256 mb) 39h thru 3fh ffh rfu
146 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) the alternate vendor-specific extended query provid es information related to the expanded command set provided by the fs-s family. the alternate query para meters use a format in which each parameter begins with an identifier byte and a parameter length byte. dr iver software can check each parameter id and can use the length value to skip to the next parameter if the parameter is not needed or not recognized by the software. table 12.26 cfi primary vendor-specific extended query byte address data description 40h 50h query-unique ascii string ?pri? 41h 52h 42h 49h 43h 31h major version number = 1, ascii 44h 33h minor version number = 3, ascii 45h 21h address sensitive unlock (bits 1-0) 00b = required, 01b = not required process technology (bits 5-2) 0000b = 0.23 m floating gate 0001b = 0.17 m floating gate 0010b = 0.23 m mirrorbit 0011b = 0.11 m floating gate 0100b = 0.11 m mirrorbit 0101b = 0.09 m mirrorbit 1000b = 0.065 m mirrorbit 46h 02h erase suspend 0 = not supported 1 = read only 2 = read and program 47h 01h sector protect 00 = not supported x = number of sectors in group 48h 00h temporary sector unprotect 00 = not supported 01 = supported 49h 08h sector protect/unprotect scheme 04 = high voltage method 05 = software command locking method 08 = advanced sector protection method 4ah 00h simultaneous operation 00 = not supported x = number of sectors 4bh 01h burst mode (synchronous sequential read) support 00 = not supported 01 = supported 4ch 03h page mode type, initial delivery configuration, user configurable for 512b page 00 = not supported 01 = 4 word read page 02 = 8-read word page 03 = 256-byte program page 04 = 512-byte program page 4dh 00h acc (acceleration) supply minimum 00 = not supported, 100 mv 4eh 00h acc (acceleration) supply maximum 00 = not supported, 100 mv 4fh 07h wp# protection 01 = whole chip 04 = uniform device with bottom wp protect 05 = uniform device with top wp protect 07 = uniform device with top or bottom write protect (user configurable) 50h 01h program suspend 00 = not supported 01 = supported
november 6, 2013 s25fs-s_00_04 s25fs-s family 147 data sheet (preliminary) table 12.27 cfi alternate vendor-specific extended query header byte address data description 51h 41h query-unique ascii string ?alt? 52h 4ch 53h 54h 54h 32h major version number = 2, ascii 55h 30h minor version number = 0, ascii table 12.28 cfi alternate vendor-specific extended query parameter 0 parameter relative byte address offset data description 00h 00h parameter id (ordering part number) 01h 10h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 53h ascii ?s? for manufacturer (spansion) 03h 32h ascii ?25? for product characters (single die spi) 04h 35h 05h 46h ascii ?fs? for interface characters (spi 1.8 volt) 06h 53h 07h 31h (128 mb) 32h (256 mb) ascii characters for density 08h 32h (128 mb) 35h (256 mb) 09h 38h (128 mb) 36h (256 mb) 0ah 53h ascii ?s? for technology (65 nm mirrorbit) 0bh ffh reserved for future use 0ch ffh 0dh ffh reserved for future use 0eh ffh 0fh ffh reserved for future use 10h xxh ascii characters for model refer to ordering information on page 151 for the model number definitions. 11h xxh table 12.29 cfi alternate vendor-specific extend ed query parameter 80h address options parameter relative byte address offset data description 00h 80h parameter id (ordering part number) 01h 01h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h ebh bits 7:5 - reserved = 111b bit 4 - address length bit in cr2v[7] - yes= 0b bit 3 - autoboot support - no = 1b bit 2 - 4 byte address instructions supported - yes= 0b bit 1 - bank address + 3-byte addres s instructions supported - no = 1b bit 0 - 3-byte address instructions supported - no = 1b
148 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) table 12.30 cfi alternate vendor-specific extended query parameter 84h suspend commands parameter relative byte address offset data description 00h 84h parameter id (suspend commands 01h 08h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 75h program suspend instruction code 03h 28h program suspend latency maximum (s) 04h 7ah program resume instruction code 05h 64h program resume to next suspend typical (s) 06h 75h erase suspend instruction code 07h 28h erase suspend latency maximum (s) 08h 7ah erase resume instruction code 09h 64h erase resume to ne xt suspend typical (s) table 12.31 cfi alternate vendor-specific extended query parameter 88h data protection parameter relative byte address offset data description 00h 88h parameter id (data protection) 01h 04h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 0ah otp size 2 n bytes, ffh = not supported 03h 01h otp address map format, 01h = fl-s and fs-s format ffh = not supported 04h xxh block protect type, model dependent 00h = fl-p, fl-s, fs-s ffh = not supported 05h xxh advanced sector protection type, model dependent 01h = fl-s and fs-s asp. table 12.32 cfi alternate vendor-specific extended query parameter 8ch reset timing parameter relative byte address offset data description 00h 8ch parameter id (reset timing) 01h 06h parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h 96h por maximum value 03h 01h por maximum exponent 2 n s 04h 23h hardware reset maximum value, ffh = not supported (the initial delivery state has hardware reset disabled but it may be enabled by the user at a later time) 05h 00h hardware reset maximum exponent 2 n s 06h 23h software reset maximum value, ffh = not supported 07h 00h software reset maximum exponent 2 n s
november 6, 2013 s25fs-s_00_04 s25fs-s family 149 data sheet (preliminary) this parameter type (parameter id f0h) may appear multiple times and have a different length each time. the parameter is used to reserve s pace in the id-cfi map or to force space (pad) to align a following parameter to a required boundary. table 12.33 cfi alternate vendor-specific extended query parameter f0h rfu parameter relative byte address offset data description 00h f0h parameter id (rfu) 01h 0fh parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter) 02h ffh rfu ... ffh rfu 10h ffh rfu table 12.34 cfi alternate vendor-specific extended query parameter a5h, jedec sfdp (sheet 1 of 2) parameter relative byte address offset sfdp relative dword address offset data description 00h n/a a5h cfi parameter id (jedec sfdp) 01h n/a 3ch parameter length (the number of following bytes in this parameter. adding this value to the current location value +1 = the first byte of the next parameter). 02h 00h jedec sfdp parameter dword-1 ffh start of sfdp jedec parameter bits 7:5 = unused = 111b bit 4 = 06h is status register write instruction = 1 bit 3 = 00h must be written to status register to enable program and erase = 1 bit 2 = program buffer > 64 bytes = 1 bits 1:0 = uniform 4-kb erase unavailable = 11b 03h ffh uniform 4-kb erase opcode = not supported = ffh 04h b2h (fsxxxsag) bah (fsxxxsds) bit 23 = unused = 1b bit 22 = supports quad out (1-1-4) read = no = 0b bit 21 = supports quad i/o (1-4-4) read = yes = 1b bit 20 = supports dual i/o (1-2-2) read = yes = 1b bit19 = supports ddr 0= no, 1 = yes bit 18:17 = number of address bytes, 3 or 4 = 01b bit 16 = supports dual out (1-1-2) read = no = 0b 05h ffh bits 31:24 = unused = ffh 06h 01h jedec sfdp parameter dword-2 ffh density in bits, zero based 07h ffh 08h ffh 09h 07h (128 mb) 0fh (256 mb) 0ah 02h jedec sfdp parameter dword-3 48h bits 7:5 = number of quad i/o (1-4-4) mode cycles = 010b bits 4:0 = number of quad i/o dummy cycles = 01000b (initial delivery state) 0bh ebh quad i/o instruction code 0ch ffh bits 23:21 = number of quad out (1-1-4) mode cycles = 111b bits 20:16 = number of quad out dummy cycles = 11111b 0dh ffh quad out instruction code 0eh 03h jedec sfdp parameter dword-4 ffh bits 7:5 = number of dual out (1-1-2) mode cycles = 111b bits 4:0 = number of dual out dummy cycles = 11111b 0fh ffh dual out instruction code 10h 88h bits 23:21 = number of dual i/o (1-2-2) mode cycles = 100b bits 20:16 = number of dual i/o dummy cycles = 01000b (initial delivery state) 11h bbh dual i/o instruction code
150 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) 12.5 initial delivery state the device is shipped from spansion with non-volatile bits set as follows: ? the entire memory array is erased: i.e. all bits are set to 1 (each byte contains ffh). ? the otp address space has the first 16 bytes progra mmed to a random number. all other bytes are erased to ffh. ? the sfdp address space contains the values as defi ned in the description of the sfdp address space. ? the id-cfi address space contains the values as defi ned in the description of the id-cfi address space. ? the status register 1 non-volatile contains 00h (all sr1nv bits are cleared to 0?s). ? the configuration register 1 non-volatile contains 00h. ? the configuration register 2 non-volatile contains 08h. ? the configuration register 3 non-volatile contains 00h. ? the configuration register 4 non-volatile contains 10h. ? the password register contains ffffffff-ffffffffh ? all ppb bits are 1. ? the asp register bits are ffffh 12h 04h jedec sfdp parameter dword-5 f6h bits 7:5 rfu = 111b bit 4 = qpi supported = yes = 1b bits 3:1 rfu = 11b bit 0 = dual all not supported = 0b 13h ffh bits 15:8 = rfu = ffh 14h ffh bits 23:16 = rfu = ffh 15h ffh bits 31:24 = rfu = ffh 16h 05h jedec sfdp parameter dword-6 ffh bits 7:0 = rfu = ffh 17h ffh bits 15:8 = rfu = ffh 18h ffh bits 23:21 = number of dual all mode cycles = 111b bits 20:16 = number of dual all dummy cycles = 11111b 19h ffh dual all instruction code 1ah 06h jedec sfdp parameter dword-7 ffh bits 7:0 = rfu = ffh 1bh ffh bits 15:8 = rfu = ffh 1ch 48h bits 23:21 = number of qpi mode cycles = 010b bits 20:16 = number of qpi dummy cycles = 01000b 1dh ebh qpi mode (4-4-4) instruction code 1eh 07h jedec sfdp parameter dword-8 0ch sector type 1 size 2 n bytes = 4-kb = 0ch for hybrid (initial delivery state) 1fh 20h sector type 1 instruction 20h 10h (128 mb) 10h (256 mb) sector type 2 size 2 n bytes = 64 kb = 10h for 128 mb and 256 mb 21h d8 sector type 2 instruction 22h 08h jedec sfdp parameter dword-9 00h sector type 3 size 2 n bytes = not supported = 00h 23h ffh sector type 3 instruction = not supported = ffh 24h 00h sector type 4 size 2 n bytes = not supported = 00h 25h ffh sector type 4 instruction = not supported = ffh table 12.34 cfi alternate vendor-specific extended query parameter a5h, jedec sfdp (sheet 2 of 2) parameter relative byte address offset sfdp relative dword address offset data description
november 6, 2013 s25fs-s_00_04 s25fs-s family 151 data sheet (preliminary) ordering information 13. ordering part number the ordering part number is formed by a valid combination of the following: s25fs 256 s ag m f i 00 1 packing type 0 = tray 1 = tube 3 = 13? tape and reel model number (additional ordering options) 00 = soic16 / wson footprint, 64-kb physical sector 10 = soic8 / wson, 64-kb physical sector 20 = 5x5 ball bga footprint, 64-kb physical sector 30 = 4x6 ball bga footprint, 64-kb physical sector 1d = soic8, 64-kb physical sector, ddr temperature range i = industrial (?40c to + 85c) v = automotive in-cabin (?40c to + 105c) package materials f = lead (pb)-free h = low-halogen, lead (pb)-free package type m = 16-pin soic / 8-lead soic n = 8-contact wson 6 x 8 mm / wson 6 x 5 mm b = 24-ball bga 6 x 8 mm package, 1.00 mm pitch speed ag = 133 mhz ds = 80 mhz ddr device technology s = 0.065 m mirrorbit process technology density 128 = 128 mbit 256 = 256 mbit device family s25fs spansion memory 1.8 volt-only, serial peripheral interface (spi) flash memory
152 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. 14. contacting spansion obtain the latest list of company locations and contact information at http://www.spansion.com/about/pages/locations.aspx. valid combinations base ordering part number speed option package and temperature model number packing type package marking s25fs128s ag mfi, mfv 10 0, 1, 3 fs128s + (temp) + f + (model number) ag nfi, nfv 10 0, 1, 3 fs128s + a + (temp) + f + (model number) ag bhi, bhv 20, 30 0, 3 fs128s + a + (temp) + h + (model number) ds mfi, mfv 1d 0, 1, 3 fs128s + (temp) + f + (model number) ds nfi, nfv 10 0, 1, 3 fs128s + d + (temp) + f + (model number) ds bhi, bhv 20, 30 0, 3 fs128s + d + (temp) + h + (model number) s25fs256s ag mfi, mfv 00 0, 1, 3 fs256s + a + (temp) + f + (model number) ag nfi, nfv 00 0, 1, 3 fs256s + a + (temp) + f + (model number) ag bhi, bhv 20, 30 0, 3 fs256s + a + (temp) + h + (model number) ds mfi, mfv 00 0, 1, 3 fs256s + d + (temp) + f + (model number) ds nfi, nfv 00 0, 1, 3 fs256s + d + (temp) + f + (model number) ds bhi, bhv 20, 30 0, 3 fs256s + d + (temp) + h + (model number)
november 6, 2013 s25fs-s_00_04 s25fs-s family 153 data sheet (preliminary) 15. revision history section description revision 01 (april 5, 2013) initial release revision 02 (april 8, 2013) initial delivery state corrected information on configuration register 2 revision 03 (august 22, 2013) global replaced ?quad all? with ?qpi? performance summary typical program and eras e rates table: corrected kbytes / s migration notes spansion spi families comparison tabl e: corrected page programming rate (typ.) for fs-s dc characteristics fs-s dc characteristics table: added i sb (automotive) sdr ac characteristics ac characteristics table: updated parameter for f sck, c registers latency code (cycles) versus frequency table: updated table added note 4 embedded algorithm performance ta b l e s program and erase performance table: corrected typ and max values for t pp ordering information added 1d and 5d to model number valid combinations table: corr ected model number for s25fs128s revision 04 (november 6, 2013) global changed data sheet designation from ?adv ance information? to ?preliminary? changed uson to wson physical interface added figure: 8-pin plastic small outline package (soic8) updated figure: 8-connector package (wson 6x5) removed figure: vsop thin 8-lead, 208 mil body width, (sov008) configuration register 4 updated output impedance control table ordering information updated model numbers and package type
154 s25fs-s family s25fs-s_00_04 november 6, 2013 data sheet (preliminary) colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2013 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse?, ornand? and combinations thereof, are trademarks and registered trademarks of spansion llc in the united states and other countries. other names used are for informational purposes only and may be trademarks of their respective owners.

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